Thin Film Transistors and Fabrication Methods Thereof
    41.
    发明申请
    Thin Film Transistors and Fabrication Methods Thereof 审中-公开
    薄膜晶体管及其制作方法

    公开(公告)号:US20110101459A1

    公开(公告)日:2011-05-05

    申请号:US13005349

    申请日:2011-01-12

    IPC分类号: H01L27/12 H01L21/336

    摘要: Thin film transistors and fabrication methods thereof. A gate is formed overlying a portion of a substrate. A first vanadium oxide layer formed overlying the gate and the substrate. A gate-insulating layer is formed overlying the first vanadium oxide layer. A semiconductor layer is formed on a portion of the gate-insulating layer. A source and a drain are formed on a portion of the semiconductor layer.

    摘要翻译: 薄膜晶体管及其制造方法。 形成覆盖衬底的一部分的栅极。 形成在栅极和衬底上的第一氧化钒层。 形成覆盖第一氧化钒层的栅极绝缘层。 半导体层形成在栅极绝缘层的一部分上。 源极和漏极形成在半导体层的一部分上。

    Nano-based gas diffusion media
    44.
    发明授权
    Nano-based gas diffusion media 失效
    纳米级气体扩散介质

    公开(公告)号:US07785748B2

    公开(公告)日:2010-08-31

    申请号:US11731968

    申请日:2007-04-02

    IPC分类号: H01M2/00 H01M4/00

    CPC分类号: H01M8/023

    摘要: The present invention relates to novel methods for producing a nano-porous gas diffusion media, compositions thereof, and devices comprising the same. The nano-porous gas diffusion media of the invention is produced using photolithographic techniques to create a solid substrate comprising a plurality of nano-scale (1 nm-300 μm) pores or holes that allow for the diffusion or exchange of molecules, gases, and/or liquids through the substrate. The nano-porous diffusion media of the invention also displays superior electro- and thermal conductivity, and increased durability and performance. In some embodiments, the nano-porous diffusion media of the invention is also coated with a self-assembling monolayer (SAM) of organic molecules to further improve its physical characteristics.

    摘要翻译: 本发明涉及制备纳米多孔气体扩散介质的新方法及其组合物及其制备方法。 使用光刻技术制造本发明的纳米多孔气体扩散介质,以产生包含多个纳米尺度(1nm-300μm)的孔或孔的固体基质,其允许分子,气体和 /或液体通过基底。 本发明的纳米多孔扩散介质还显示出优异的导电性和导热性,并且增加了耐久性和性能。 在一些实施方案中,本发明的纳米多孔扩散介质还涂覆有有机分子的自组装单层(SAM)以进一步改善其物理特性。

    Thin film transistor and method for fabricating same
    45.
    发明授权
    Thin film transistor and method for fabricating same 有权
    薄膜晶体管及其制造方法

    公开(公告)号:US07777231B2

    公开(公告)日:2010-08-17

    申请号:US12432735

    申请日:2009-04-29

    IPC分类号: H01L21/02

    摘要: A method for forming a thin film transistor on a substrate is disclosed. A gate electrode and a gate insulation layer are disposed on a surface of the substrate. A deposition process is performed by utilizing hydrogen diluted silane to form a silicon-contained thin film on the gate insulation layer first. A hydrogen plasma etching process is thereafter performed. The deposition process and the etching process are repeated for at least one time to form an interface layer. Finally, an amorphous silicon layer, n+ doped Si layers, a source electrode, and a drain electrode are formed on the interface layer.

    摘要翻译: 公开了一种在衬底上形成薄膜晶体管的方法。 栅电极和栅极绝缘层设置在基板的表面上。 首先通过利用氢稀释的硅烷在栅极绝缘层上形成含硅薄膜来进行沉积工艺。 此后执行氢等离子体蚀刻工艺。 重复沉积工艺和蚀刻工艺至少一次以形成界面层。 最后,在界面层上形成非晶硅层,n +掺杂Si层,源电极和漏电极。

    HIGH DENSITY HIGH PERFORMANCE POWER TRANSISTOR LAYOUT
    46.
    发明申请
    HIGH DENSITY HIGH PERFORMANCE POWER TRANSISTOR LAYOUT 审中-公开
    高密度高性能功率晶体管布局

    公开(公告)号:US20090289299A1

    公开(公告)日:2009-11-26

    申请号:US12125070

    申请日:2008-05-22

    IPC分类号: H01L29/78

    摘要: A power transistor comprises a gate region, a source region, and a drain region. The gate region comprises a first line portion, a second line portion, and a third line portion. The first line portion couples to the second line portion so as to form a first V-shaped structure. The second line portion couples to the third line portion so as to form a second V-shaped structure. The first line portion, the second line portion, and the third line portion form a N-shaped structure.

    摘要翻译: 功率晶体管包括栅极区域,源极区域和漏极区域。 栅极区域包括第一线部分,第二线部分和第三线部分。 第一线部分耦合到第二线部分以形成第一V形结构。 第二线部分耦合到第三线部分以形成第二V形结构。 第一线部分,第二线部分和第三线部分形成N形结构。

    THIN FILM TRANSISTOR AND METHOD FOR FABRICATING SAME
    47.
    发明申请
    THIN FILM TRANSISTOR AND METHOD FOR FABRICATING SAME 有权
    薄膜晶体管及其制造方法

    公开(公告)号:US20090212289A1

    公开(公告)日:2009-08-27

    申请号:US12432735

    申请日:2009-04-29

    IPC分类号: H01L29/786

    摘要: A method for forming a thin film transistor on a substrate is disclosed. A gate electrode and a gate insulation layer are disposed on a surface of the substrate. A deposition process is performed by utilizing hydrogen diluted silane to form a silicon-contained thin film on the gate insulation layer first. A hydrogen plasma etching process is thereafter performed. The deposition process and the etching process are repeated for at least one time to form an interface layer. Finally, an amorphous silicon layer, n+ doped Si layers, a source electrode, and a drain electrode are formed on the interface layer.

    摘要翻译: 公开了一种在衬底上形成薄膜晶体管的方法。 栅电极和栅极绝缘层设置在基板的表面上。 首先通过利用氢稀释的硅烷在栅极绝缘层上形成含硅薄膜来进行沉积工艺。 此后执行氢等离子体蚀刻工艺。 重复沉积工艺和蚀刻工艺至少一次以形成界面层。 最后,在界面层上形成非晶硅层,n +掺杂Si层,源电极和漏电极。

    Thin film transistor and method for fabricating same
    48.
    发明授权
    Thin film transistor and method for fabricating same 有权
    薄膜晶体管及其制造方法

    公开(公告)号:US07541229B2

    公开(公告)日:2009-06-02

    申请号:US10904377

    申请日:2004-11-07

    IPC分类号: H01L21/00 H01L21/84

    摘要: A method for forming a thin film transistor on a substrate is disclosed. A gate electrode and a gate insulation layer are disposed on a surface of the substrate. A deposition process is performed by utilizing hydrogen diluted silane to form a silicon-contained thin film on the gate insulation layer first. A hydrogen plasma etching process is thereafter performed. The deposition process and the etching process are repeated for at least one time to form an interface layer. Finally, an amorphous silicon layer, n+ doped Si layers, a source electrode, and a drain electrode are formed on the interface layer.

    摘要翻译: 公开了一种在衬底上形成薄膜晶体管的方法。 栅电极和栅极绝缘层设置在基板的表面上。 首先通过利用氢稀释的硅烷在栅极绝缘层上形成含硅薄膜来进行沉积工艺。 此后执行氢等离子体蚀刻工艺。 重复沉积工艺和蚀刻工艺至少一次以形成界面层。 最后,在界面层上形成非晶硅层,n +掺杂Si层,源电极和漏电极。

    PHOTO DETECTOR AND METHOD FOR FABRICATING THE SAME
    50.
    发明申请
    PHOTO DETECTOR AND METHOD FOR FABRICATING THE SAME 有权
    照片检测器及其制造方法

    公开(公告)号:US20090027371A1

    公开(公告)日:2009-01-29

    申请号:US11943602

    申请日:2007-11-21

    IPC分类号: G09G3/00 H01L31/18 H01L31/062

    摘要: A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer with a first state, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer with a second state, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region of the substrate. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer.

    摘要翻译: 公开了一种光电检测器。 光检测器包括基板,具有第一状态的第一图案化半导体层,电介质层,图案化导电层,层间电介质,具有第二状态的第二图案化半导体层,设置在第二状态的第二图案化半导体层, 层电介质和设置在第二半导体层的部分上的两个第二电极。 具有第一掺杂区域和第二掺杂区域的第一图案化半导体层设置在衬底的晶体管区域上。 介电层设置成覆盖基板和第一半导体层,图案化的导电层设置在电介质层上,并且具有适于暴露第一掺杂区和第二掺杂区的至少两个开口的层间电介质是 被设置成覆盖电介质层。 第二图案化半导体层设置在光敏区域上,并且第一电极电连接到第一图案化半导体层。