Method of fabricating thin film transistor
    1.
    发明授权
    Method of fabricating thin film transistor 有权
    制造薄膜晶体管的方法

    公开(公告)号:US07378303B2

    公开(公告)日:2008-05-27

    申请号:US11467940

    申请日:2006-08-29

    IPC分类号: H01L21/84

    CPC分类号: H01L29/66765 H01L29/458

    摘要: A method for fabricating a thin film transistor is provided. A conductive layer is formed on a substrate. A patterned mask is formed on the conductive layer to cover a predetermined thin film transistor (TFT) area, and at least one portion of the conductive layer exposed by the patterned mask are removed. A laser is applied to form a laser hole in the patterned mask to expose a portion of the conductive layer and the laser hole substantially corresponds to a channel region of the predetermined TFT area. The exposed conductive layer is etched to form source and drain electrodes on opposite sides of the channel region.

    摘要翻译: 提供一种制造薄膜晶体管的方法。 在基板上形成导电层。 在导电层上形成图案化掩模以覆盖预定的薄膜晶体管(TFT)区域,并且去除由图案化掩模暴露的导电层的至少一部分。 施加激光以在图案化掩模中形成激光孔,以暴露导电层的一部分,并且激光孔基本对应于预定TFT区域的沟道区域。 蚀刻暴露的导电层以在沟道区域的相对侧上形成源极和漏极。

    Method of forming a thin film transistor
    3.
    发明授权
    Method of forming a thin film transistor 有权
    形成薄膜晶体管的方法

    公开(公告)号:US07253041B2

    公开(公告)日:2007-08-07

    申请号:US11142931

    申请日:2005-06-02

    IPC分类号: H01L21/84

    摘要: A method of forming a thin film transistor comprising a deposition procedure of a microcrystal material layer and performing a plasma treatment procedure. The deposition procedure and the plasma treatment procedure are repeated. A buffer layer is thus formed on the gate electrode.

    摘要翻译: 一种形成薄膜晶体管的方法,包括微晶材料层的沉积程序并执行等离子体处理程序。 重复沉积程序和等离子体处理程序。 因此,在栅电极上形成缓冲层。

    Methods and apparatuses for fabricating thin film transistors
    5.
    发明申请
    Methods and apparatuses for fabricating thin film transistors 审中-公开
    用于制造薄膜晶体管的方法和装置

    公开(公告)号:US20060111243A1

    公开(公告)日:2006-05-25

    申请号:US11143155

    申请日:2005-06-02

    IPC分类号: H01L39/14

    CPC分类号: H01L29/4908 H01L29/66765

    摘要: Methods and apparatuses for fabricating thin film transistors. An apparatus comprises a first chamber and a second chamber. A substrate comprising a metal gate formed thereon is brought into the first chamber to form a passivation layer on the metal gate. The substrate is then transported to the second chamber to form a gate insulating layer and a semiconductor layer on the passivation layer. Accordingly, the second chamber experiences no metal contamination resulting from the metal gate.

    摘要翻译: 用于制造薄膜晶体管的方法和装置。 一种装置包括第一室和第二室。 将其上形成有金属栅的衬底带入第一室中,以在金属栅上形成钝化层。 然后将衬底输送到第二室,以在钝化层上形成栅极绝缘层和半导体层。 因此,第二室没有经历金属栅极产生的金属污染。

    Methods for fabricating thin film transistors
    7.
    发明申请
    Methods for fabricating thin film transistors 审中-公开
    制造薄膜晶体管的方法

    公开(公告)号:US20060111244A1

    公开(公告)日:2006-05-25

    申请号:US11143698

    申请日:2005-06-02

    IPC分类号: H01L39/14

    CPC分类号: H01L29/66765 H01L29/4908

    摘要: A fabrication method of thin film transistor. A patterned gate is formed on an insulator substrate. A buffer layer is formed on the insulating substrate. The patterned gate is formed by plasma enhanced chemical vapor deposition (PECVD) using a mixture of silane, argon, nitrogen to serve as reactants at a temperature of approximately 20-200° C. A gate insulating layer is formed on the buffer layer. A semiconductor layer is formed on the gate insulating layer. A source/drain layer is formed on the semiconductor layer. The buffer layer protects the metal gate from damage during subsequent plasma enhanced chemical vapor deposition.

    摘要翻译: 薄膜晶体管的制造方法。 图案化栅极形成在绝缘体基板上。 在绝缘基板上形成缓冲层。 图案化的栅极通过使用硅烷,氩,氮的混合物的等离子体增强化学气相沉积(PECVD)形成,以在约20-200℃的温度下用作反应物。在缓冲层上形成栅极绝缘层。 在栅极绝缘层上形成半导体层。 源极/漏极层形成在半导体层上。 缓冲层在随后的等离子体增强化学气相沉积期间保护金属栅极免受损坏。

    Methods for fabricating thin film transistors
    8.
    发明申请
    Methods for fabricating thin film transistors 有权
    制造薄膜晶体管的方法

    公开(公告)号:US20060110871A1

    公开(公告)日:2006-05-25

    申请号:US11142930

    申请日:2005-06-02

    IPC分类号: H01L21/8234

    摘要: Fabrication methods for thin film transistors. A metal gate stack structure is formed on an insulating substrate. The substrate is performed using thermal annealing to create an oxide layer on the sidewalls of the metal gate stack structure. A gate insulating layer is formed on the substrate covering the metal gate stack structure. A semiconductor layer is formed on the gate insulating layer. A source/drain layer is formed on the semiconductor.

    摘要翻译: 薄膜晶体管的制造方法。 在绝缘基板上形成金属栅堆叠结构。 使用热退火进行衬底,以在金属栅极堆叠结构的侧壁上产生氧化物层。 在覆盖金属栅堆叠结构的基板上形成栅极绝缘层。 在栅极绝缘层上形成半导体层。 在半导体上形成源极/漏极层。

    Method for fabricating thin film transistors
    9.
    发明申请
    Method for fabricating thin film transistors 审中-公开
    制造薄膜晶体管的方法

    公开(公告)号:US20060110866A1

    公开(公告)日:2006-05-25

    申请号:US11142928

    申请日:2005-06-02

    IPC分类号: H01L21/00

    摘要: Thin film transistor fabrication methods. A gate electrode is formed on a substrate. The surface of metal gate is subjected to a hydrogen plasma treatment to remove a native oxide formed thereon. A nitride layer as a buffer layer is formed to cover the metal gate. A gate insulating layer is formed on the buffer layer. A semiconductor layer is formed on the gate insulating layer. A source/drain layer is formed on the semiconductor layer. The buffer layer prevents the metal gate from damage in subsequent plasma enhanced chemical vapor deposition processes.

    摘要翻译: 薄膜晶体管制造方法。 在基板上形成栅电极。 对金属栅极的表面进行氢等离子体处理以除去其上形成的天然氧化物。 形成作为缓冲层的氮化物层以覆盖金属栅极。 在缓冲层上形成栅极绝缘层。 在栅极绝缘层上形成半导体层。 源极/漏极层形成在半导体层上。 缓冲层防止金属栅极在随后的等离子体增强化学气相沉积工艺中损坏。

    Method of forming a thin film transistor
    10.
    发明申请
    Method of forming a thin film transistor 有权
    形成薄膜晶体管的方法

    公开(公告)号:US20060110862A1

    公开(公告)日:2006-05-25

    申请号:US11142931

    申请日:2005-06-02

    IPC分类号: H01L21/84

    摘要: A method of forming a thin film transistor comprising a deposition procedure of a microcrystal material layer and performing a plasma treatment procedure. The deposition procedure and the plasma treatment procedure are repeated. A buffer layer is thus formed on the gate electrode.

    摘要翻译: 一种形成薄膜晶体管的方法,包括微晶材料层的沉积程序并执行等离子体处理程序。 重复沉积程序和等离子体处理程序。 因此,在栅电极上形成缓冲层。