Radio-frequency apparatus and associated methods
    41.
    发明授权
    Radio-frequency apparatus and associated methods 有权
    射频设备及相关方法

    公开(公告)号:US08467483B2

    公开(公告)日:2013-06-18

    申请号:US10388206

    申请日:2003-03-13

    CPC classification number: H04B1/0007 H04B1/0003 H04B1/0039 H04B1/28 H04B1/406

    Abstract: A radio-frequency apparatus includes an integrated circuit. The integrated circuit includes receiver analog circuitry, receiver digital circuitry, a digital-to-analog converter, and a signal selector. The receiver analog circuitry receives radio-frequency signals, and provides a first digital signal. The receiver digital circuitry receives the first digital signal, and provides a second digital signal. The digital-to-analog converter converts the second digital signal into a first analog signal. The signal selector receives the second digital signal and the first analog signal, and selectively provides one of the second digital signal and the first analog signal as an output signal of the integrated circuit.

    Abstract translation: 射频装置包括集成电路。 集成电路包括接收机模拟电路,接收机数字电路,数模转换器和信号选择器。 接收机模拟电路接收射频信号,并提供第一数字信号。 接收机数字电路接收第一数字信号,并提供第二数字信号。 数模转换器将第二数字信号转换为第一模拟信号。 信号选择器接收第二数字信号和第一模拟信号,并且选择性地提供第二数字信号和第一模拟信号中的一个作为集成电路的输出信号。

    Receiver architectures for digital radio broadcasts and associated methods
    43.
    发明授权
    Receiver architectures for digital radio broadcasts and associated methods 有权
    数字无线电广播接收机架构及相关方法

    公开(公告)号:US08195115B2

    公开(公告)日:2012-06-05

    申请号:US13111623

    申请日:2011-05-19

    CPC classification number: H04H40/18 H04B1/1646 H04B1/3805 H04B1/406

    Abstract: Receiver architectures and related methods are disclosed for high definition (HD) and digital radio FM broadcast receivers. The radio receiver architectures are configured to utilize multiple analog-to-digital converters (ADCs) to handle the digital radio spectrum and can be configured to modify a target IF frequencies depending upon the mode of operation of the receiver. For example, the receiver can include an analog FM reception mode and a digital FM reception mode for which different down-conversions are used for the same analog-plus-digital audio broadcast channel. If desired, the radio broadcast receivers disclosed can be configured so that they only receive digital FM radio content, for example, if the analog FM broadcast was of no interest and/or if the broadcast was all digital.

    Abstract translation: 公开了用于高分辨率(HD)和数字无线电FM广播接收机的接收机架构和相关方法。 无线电接收器架构被配置为利用多个模数转换器(ADC)来处理数字无线电频谱,并且可以被配置为根据接收机的操作模式来修改目标IF频率。 例如,接收机可以包括模拟FM接收模式和数字FM接收模式,对于相同的模拟 - 数字音频广播频道,接收模式和不同的下变频被使用。 如果需要,所公开的无线电广播接收机可以被配置为使得它们仅接收数字FM无线电内容,例如,如果模拟FM广播不感兴趣和/或如果广播是全部数字的。

    RECEIVER ARCHITECTURES FOR DIGITAL RADIO BROADCASTS AND ASSOCIATED METHODS
    44.
    发明申请
    RECEIVER ARCHITECTURES FOR DIGITAL RADIO BROADCASTS AND ASSOCIATED METHODS 有权
    数字无线电广播接收机架构及相关方法

    公开(公告)号:US20110216855A1

    公开(公告)日:2011-09-08

    申请号:US13111623

    申请日:2011-05-19

    CPC classification number: H04H40/18 H04B1/1646 H04B1/3805 H04B1/406

    Abstract: Receiver architectures and related methods are disclosed for high definition (HD) and digital radio FM broadcast receivers. The radio receiver architectures are configured to utilize multiple analog-to-digital converters (ADCs) to handle the digital radio spectrum and can be configured to modify a target IF frequencies depending upon the mode of operation of the receiver. For example, the receiver can include an analog FM reception mode and a digital FM reception mode for which different down-conversions are used for the same analog-plus-digital audio broadcast channel. If desired, the radio broadcast receivers disclosed can be configured so that they only receive digital FM radio content, for example, if the analog FM broadcast was of no interest and/or if the broadcast was all digital.

    Abstract translation: 公开了用于高分辨率(HD)和数字无线电FM广播接收机的接收机架构和相关方法。 无线电接收器架构被配置为利用多个模数转换器(ADC)来处理数字无线电频谱,并且可以被配置为根据接收机的操作模式来修改目标IF频率。 例如,接收机可以包括模拟FM接收模式和数字FM接收模式,对于相同的模拟 - 数字音频广播频道,接收模式和不同的下变频被使用。 如果需要,所公开的无线电广播接收机可以被配置为使得它们仅接收数字FM无线电内容,例如,如果模拟FM广播不感兴趣和/或如果广播全部是数字的。

    Receiver architectures for digital radio broadcasts and associated methods
    45.
    发明授权
    Receiver architectures for digital radio broadcasts and associated methods 有权
    数字无线电广播接收机架构及相关方法

    公开(公告)号:US07949319B2

    公开(公告)日:2011-05-24

    申请号:US11726500

    申请日:2007-03-22

    CPC classification number: H04H40/18 H04B1/1646 H04B1/3805 H04B1/406

    Abstract: Receiver architectures and related methods are disclosed for high definition (HD) and digital radio FM broadcast receivers. The radio receiver architectures are configured to utilize multiple analog-to-digital converters (ADCs) to handle the digital radio spectrum and can be configured to modify a target IF frequencies depending upon the mode of operation of the receiver. For example, the receiver can include an analog FM reception mode and a digital FM reception mode for which different down-conversions are used for the same analog-plus-digital audio broadcast channel. If desired, the radio broadcast receivers disclosed can be configured so that they only receive digital FM radio content, for example, if the analog FM broadcast was of no interest and/or if the broadcast was all digital.

    Abstract translation: 公开了用于高分辨率(HD)和数字无线电FM广播接收机的接收机架构和相关方法。 无线电接收器架构被配置为利用多个模数转换器(ADC)来处理数字无线电频谱,并且可以被配置为根据接收机的操作模式来修改目标IF频率。 例如,接收机可以包括模拟FM接收模式和数字FM接收模式,对于相同的模拟 - 数字音频广播频道,接收模式和不同的下变频被使用。 如果需要,所公开的无线电广播接收机可以被配置为使得它们仅接收数字FM无线电内容,例如,如果模拟FM广播不感兴趣和/或如果广播全部是数字的。

    Mechanism for controlling amplifier gain in a radio receiver
    46.
    发明授权
    Mechanism for controlling amplifier gain in a radio receiver 失效
    控制无线电接收机放大器增益的机制

    公开(公告)号:US07890075B2

    公开(公告)日:2011-02-15

    申请号:US11648413

    申请日:2006-12-29

    CPC classification number: H03G3/3068

    Abstract: A radio receiver such as a frequency modulation (FM) receiver, for example, includes a radio frequency (RF) amplifier having an adjustable gain output. The RF amplifier may be configured to receive and amplify an incoming RF signal. The receiver also includes an intermediate frequency (IF) amplifier having an adjustable gain output. The IF amplifier may be configured to receive and amplify an IF signal that corresponds to the RF signal. The receiver also includes a gain control unit that is coupled to the RF amplifier and the IF amplifier. The gain control unit may be configured to independently adjust the gain of each of the RF amplifier and the IF amplifier, dependent upon a peak output level of both the RF amplifier and the IF amplifier.

    Abstract translation: 诸如调频(FM)接收机的无线电接收机例如包括具有可调增益输出的射频(RF)放大器。 RF放大器可以被配置为接收和放大输入RF信号。 接收机还包括具有可调增益输出的中频(IF)放大器。 IF放大器可以被配置为接收和放大对应于RF信号的IF信号。 接收机还包括耦合到RF放大器和IF放大器的增益控制单元。 增益控制单元可以被配置为独立地调节每个RF放大器和IF放大器的增益,这取决于RF放大器和IF放大器的峰值输出电平。

    INPUT STAGE FOR AN AMPLIFIER
    47.
    发明申请
    INPUT STAGE FOR AN AMPLIFIER 有权
    输入级放大器

    公开(公告)号:US20100120391A1

    公开(公告)日:2010-05-13

    申请号:US12692730

    申请日:2010-01-25

    CPC classification number: H04B1/18 H03F3/45183

    Abstract: In one embodiment, the present invention includes an amplifier having an input to receive a radio frequency (RF) signal from an output node of a source. An input stage coupled to the amplifier input may include one or more components to aid in processing of incoming signals. One such component coupled between the source and the input of the amplifier is a coupling capacitor used to maintain a bias voltage of the amplifier at a different potential than a DC voltage of the output node. In certain applications, the amplifier and the coupling capacitor may be integrated on a single substrate.

    Abstract translation: 在一个实施例中,本发明包括具有用于从源的输出节点接收射频(RF)信号的输入的放大器。 耦合到放大器输入的输入级可以包括一个或多个组件以帮助处理输入信号。 耦合在放大器的源极和输入之间的一个这样的部件是用于将放大器的偏置电压保持在与输出节点的直流电压不同的电位的耦合电容器。 在某些应用中,放大器和耦合电容器可以集成在单个衬底上。

    Digital architecture for radio-frequency apparatus and associated methods
    48.
    发明授权
    Digital architecture for radio-frequency apparatus and associated methods 有权
    射频设备数字架构及相关方法

    公开(公告)号:US07702362B2

    公开(公告)日:2010-04-20

    申请号:US11287995

    申请日:2005-11-28

    Abstract: A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry. The receiver analog circuitry resides within a first integrated circuit and the receiver digital circuitry resides within a second integrated circuit. The second integrated circuit couples to the first integrated circuit via a one-bit digital interface. The receiver analog circuitry receives an RF signal and processes the received RF signal to generate a digital signal. The receiver analog circuitry provides the digital signal to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal with an intermediate frequency (IF) local oscillator (LO) signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal.

    Abstract translation: 射频(RF)接收机包括接收机模拟电路和接收机数字电路。 接收器模拟电路驻留在第一集成电路内,并且接收器数字电路位于第二集成电路内。 第二集成电路通过一位数字接口耦合到第一集成电路。 接收机模拟电路接收RF信号并处理所接收的RF信号以产生数字信号。 接收机模拟电路将数字信号提供给接收机数字电路。 接收机数字电路包括数字下变频器电路,其将数字信号与中频(IF)本地振荡器(LO)信号混合以产生数字下变频信号。 接收机数字电路还包括数字滤波器电路,其对数字下变频信号进行滤波以产生经滤波的数字信号。

    Digital Architecture Using One-Time Programmable (OTP) Memory
    50.
    发明申请
    Digital Architecture Using One-Time Programmable (OTP) Memory 有权
    使用一次性可编程(OTP)存储器的数字架构

    公开(公告)号:US20100009640A1

    公开(公告)日:2010-01-14

    申请号:US12562357

    申请日:2009-09-18

    CPC classification number: G06F8/60

    Abstract: In one aspect, the present invention includes an apparatus having a digital signal processor (DSP), a controller coupled to the DSP to provide control signals to the DSP, and a one-time programmable (OTP) memory coupled to the DSP and the controller. The OTP memory may include multiple code portions including a first code block to control the DSP and a second code block to control the controller.

    Abstract translation: 一方面,本发明包括具有数字信号处理器(DSP)的装置,耦合到DSP以向DSP提供控制信号的控制器以及耦合到DSP和控制器的一次可编程(OTP)存储器 。 OTP存储器可以包括多个代码部分,包括用于控制DSP的第一代码块和用于控制控制器的第二代码块。

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