公开(公告)号：US08601327B2

公开(公告)日：2013-12-03

申请号：US12944156

申请日：2010-11-11

申请人： Mun-Phil Park

发明人： Mun-Phil Park

IPC分类号： G11C29/00

CPC分类号： G11C5/025 ,  G11C17/16 ,  G11C29/785 ,  G11C29/808 ,  G11C29/846

摘要： A semiconductor memory device having a bank including a redundancy cell block and a plurality of normal cell blocks includes a plurality of normal data inputting/outputting units configured to respectively input/output data from the normal cell blocks in response to a first input/output strobe signal, a redundancy data inputting/outputting unit configured to input/output data from the redundancy cell block in response to the first input/output strobe signal, and a connection selecting unit configured to selectively connect the normal data inputting/outputting units and the redundancy data inputting/outputting unit to a plurality of local data lines in response to a address.

摘要翻译： 具有包括冗余单元块和多个正常单元块的单元的半导体存储器件包括：多个正常数据输入/输出单元，被配置为分别响应于第一输入/输出选通信号从正常单元块输入/输出数据 信号，冗余数据输入/输出单元，被配置为响应于第一输入/输出选通信号从冗余单元块输入/输出数据;以及连接选择单元，被配置为选择性地连接正常数据输入/输出单元和冗余 数据输入/输出单元响应于地址到多个本地数据线。

公开(公告)号：US07885127B2

公开(公告)日：2011-02-08

申请号：US12327404

申请日：2008-12-03

申请人： Mun Phil Park

发明人： Mun Phil Park

IPC分类号： G11C7/00

CPC分类号： G11C8/12 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

摘要： A semiconductor memory device includes a reference strobe signal generator configured to generate a reference strobe signal having a reference pulse width in response to a bank information signal and a column command signal, and a main strobe signal generator configured to generate a main strobe signal by controlling the reference pulse width in response to the reference strobe signal and a bank grouping signal that is activated in a bank grouping mode where columns are continuously accessed in a plurality of logically grouped banks.

摘要翻译： 一种半导体存储器件，包括：参考选通信号发生器，被配置为响应于存储体信息信号和列命令信号产生具有参考脉冲宽度的参考选通信号;以及主选通信号发生器，其被配置为通过控制来产生主选通信号 响应于参考选通信号的参考脉冲宽度和在以多个逻辑分组的存储体中连续访问列的存储体分组模式中激活的存储体分组信号。

公开(公告)号：US07782704B2

公开(公告)日：2010-08-24

申请号：US11826650

申请日：2007-07-17

申请人： Mun-Phil Park

发明人： Mun-Phil Park

IPC分类号： G11C8/00

CPC分类号： G11C8/10

摘要： A column decoder includes: a plurality of main decoding units coupled to different memory banks that decode a pre-decoding signal and output column selection signals to the corresponding memory banks; and one or more pre-decoders, having a lesser number than the main decoders, which generates and outputs the pre-decoding signal by decoding the column address and the bank information signal.

摘要翻译： 列解码器包括：耦合到不同存储体的多个主解码单元，其解码预解码信号并将列选择信号输出到对应的存储体; 以及一个或多个预解码器，其具有比主解码器更小的数字，其通过解码列地址和存储体信息信号来产生并输出预解码信号。

公开(公告)号：US07663951B2

公开(公告)日：2010-02-16

申请号：US11647393

申请日：2006-12-29

申请人： Mun-Phil Park

发明人： Mun-Phil Park

IPC分类号： G11C7/00

CPC分类号： G11C11/4094

摘要： A semiconductor memory apparatus includes a main bank configured to combine a first sub bank and a second sub bank. A center bitline sense amplifier array is arranged in a region where the first sub bank meets the second sub bank. A first precharge section is arranged above the first sub bank and a second precharge section is arranged below the second sub bank. The first precharge section precharges local input/output lines of the first sub bank and the second sub bank and the second precharge section precharges the local input/output lines.

摘要翻译： 一种半导体存储装置，包括：一个主存储体，被配置为组合第一子存储体和第二子存储体。 中心位线读出放大器阵列布置在第一子银行与第二子库相遇的区域中。 第一预充电部分布置在第一子库的上方，第二预充电部分布置在第二子库的下方。 第一预充电部对第一子库和第二子库的本地输入/输出线进行预充电，而第二预充电部对本地输入/输出线进行预充电。

公开(公告)号：US07417912B2

公开(公告)日：2008-08-26

申请号：US11585096

申请日：2006-10-24

申请人： Mun-Phil Park

发明人： Mun-Phil Park

IPC分类号： G11C7/00

CPC分类号： G11C7/08 ,  G11C7/02 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4091 ,  G11C2207/065 ,  G11C2211/4065 ,  G11C2211/4068

摘要： In a memory device that operates at high speed, a bit-line sense amplifier driver is provided to overdrive a sense amplifier in a refresh mode. A bit-line sense amplifier driver includes a refresh overdriving control unit that is coupled to an external power supply terminal and a sense amplifier power line signal output terminal, and driven by a refresh flag signal and a sense amplifier power line enable signal to apply an external supply voltage to the sense amplifier power line signal output terminal in a refresh mode.Therefore, it is possible to prevent a driving voltage from serving as noise, which hinders the high speed operation of the memory device.

摘要翻译： 在高速运行的存储器件中，提供位线读出放大器驱动器以在刷新模式下过驱动读出放大器。 位线读出放大器驱动器包括刷新过驱动控制单元，其耦合到外部电源端子和感测放大器电力线信号输出端子，并由刷新标志信号和读出放大器电力线使能信号驱动以施加 外部电源电压到感应放大器电源线信号输出端子处于刷新模式。 因此，可以防止驱动电压作为噪声，这阻碍了存储器件的高速操作。

公开(公告)号：US20080159023A1

公开(公告)日：2008-07-03

申请号：US11775986

申请日：2007-07-11

申请人： Mun Phil Park

发明人： Mun Phil Park

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1027 ,  G11C7/22 ,  G11C8/06

摘要： The present invention relates to a semiconductor memory device with a fixed burst length, including a column control circuit, the semiconductor memory device including: a command decoder decoding external commands to be output as an internal command with fixed burst length information; a column controlling unit giving a bank address to the internal command to be output as a column control signal; and a bank controlling a read and write operation corresponding to the fixed burst length in accordance with on the column control signal.

摘要翻译： 本发明涉及一种具有固定突发长度的半导体存储器件，包括列控制电路，该半导体存储器件包括：命令解码器，解码作为具有固定突发长度信息的内部命令输出的外部命令; 列控制单元，给出要作为列控制信号输出的内部命令的存储体地址; 以及根据列控制信号控制与固定突发长度对应的读写操作的存储体。

公开(公告)号：US20070104008A1

公开(公告)日：2007-05-10

申请号：US11585096

申请日：2006-10-24

申请人： Mun Phil Park

发明人： Mun Phil Park

IPC分类号： G11C7/00

CPC分类号： G11C7/08 ,  G11C7/02 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4091 ,  G11C2207/065 ,  G11C2211/4065 ,  G11C2211/4068

摘要： In a memory device that operates at high speed, a bit-line sense amplifier driver is provided to overdrive a sense amplifier in a refresh mode. A bit-line sense amplifier driver includes a refresh overdriving control unit that is coupled to an external power supply terminal and a sense amplifier power line signal output terminal, and driven by a refresh flag signal and a sense amplifier power line enable signal to apply an external supply voltage to the sense amplifier power line signal output terminal in a refresh mode. Therefore, it is possible to prevent a driving voltage from serving as noise, which hinders the high speed operation of the memory device.

摘要翻译： 在高速运行的存储器件中，提供位线读出放大器驱动器以在刷新模式下过驱动读出放大器。 位线读出放大器驱动器包括刷新过驱动控制单元，其耦合到外部电源端子和感测放大器电力线信号输出端子，并由刷新标志信号和读出放大器电力线使能信号驱动以施加 外部电源电压到感应放大器电源线信号输出端子处于刷新模式。 因此，可以防止驱动电压作为噪声，这阻碍了存储器件的高速操作。