公开(公告)号：US08379473B2

公开(公告)日：2013-02-19

申请号：US12614867

申请日：2009-11-09

申请人： Kwi-Dong Kim ,  Mun-Phil Park ,  Sung-Ho Kim

发明人： Kwi-Dong Kim ,  Mun-Phil Park ,  Sung-Ho Kim

IPC分类号： G11C8/00

CPC分类号： G11C7/10 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4096

摘要： A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks through a common data line in response to access information of the first and second memory banks.

摘要翻译： 半导体存储器件包括分别响应于第一和第二存储体选通信号而对第一和第二存储体执行数据写入操作的第一和第二写入驱动块，以及用于将数据传输到第一和第二写入的公共输入驱动块 驱动块通过公共数据线响应于第一和第二存储体的访问信息。

公开(公告)号：US08305837B2

公开(公告)日：2012-11-06

申请号：US13243590

申请日：2011-09-23

申请人： Mun-Phil Park

发明人： Mun-Phil Park

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C7/222

摘要： A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.

公开(公告)号：US08233338B2

公开(公告)日：2012-07-31

申请号：US12792444

申请日：2010-06-02

申请人： Kwi-Dong Kim ,  Mun-Phil Park ,  Sung-Ho Kim

发明人： Kwi-Dong Kim ,  Mun-Phil Park ,  Sung-Ho Kim

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C29/26 ,  G11C2029/2602

摘要： A multi-bit test control circuit includes an operation unit, a delay unit, and a generation unit. The operation unit is configured to combine a single source signal inputted to each bank with a delay signal generated by delaying the source signal by a certain time to generate a first pulse signal. The delay unit is configured to delay the first pulse signal by a certain time. The generation unit is configured to combine an output signal of the operation unit with an output signal of the delay unit to generate a second pulse signal for a bank interleaving multi-bit test.

摘要翻译： 多位测试控制电路包括操作单元，延迟单元和生成单元。 操作单元被配置为将输入到每个存储体的单个源信号与通过将源信号延迟一定时间而产生的延迟信号组合以产生第一脉冲信号。 延迟单元被配置为将第一脉冲信号延迟一定时间。 生成单元被配置为将操作单元的输出信号与延迟单元的输出信号组合，以产生用于存储体交叉多位测试的第二脉冲信号。

公开(公告)号：US20120014205A1

公开(公告)日：2012-01-19

申请号：US13243590

申请日：2011-09-23

申请人： Mun-Phil PARK

发明人： Mun-Phil PARK

IPC分类号： G11C8/18

CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C7/222

摘要： A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.

摘要翻译： 半导体器件包括：系统时钟输入单元，被配置为接收用于同步地址信号的输入时间和来自存储器控制器的命令信号的系统时钟;数据时钟输入单元，被配置为接收第一和第二数据时钟，用于使输入/ 来自存储器控制器的数据信号的输出时间，其中根据训练信息信号偏移第二数据时钟的相位，并且具有移位相位的第二数据时钟被输入到数据时钟输入单元，并且相位检测 单元，被配置为基于第一数据时钟的边缘来检测第二数据时钟的逻辑电平，并且生成训练信息信号，以根据检测到的逻辑电平将生成的信号发送到存储器控制器。

公开(公告)号：US08081524B2

公开(公告)日：2011-12-20

申请号：US11819261

申请日：2007-06-26

申请人： Mun-Phil Park

发明人： Mun-Phil Park

IPC分类号： G11C5/14

CPC分类号： G11C5/145 ,  G11C11/4074

摘要： A combo semiconductor memory apparatus capable of reducing current and power consumption is provided. The semiconductor memory apparatus includes: a signal generator that generates a voltage control signal according to the level of an external voltage; and a voltage generator that pumps up the level of the external voltage in response to the voltage control signal and outputs the pumped voltage to a high-level voltage output terminal, or supplies the external voltage as a high-level voltage.

摘要翻译： 提供能够降低电流和功耗的组合半导体存储装置。 半导体存储装置包括：信号发生器，其根据外部电压的电平生成电压控制信号; 以及电压发生器，其响应于电压控制信号提升外部电压的电平，并将泵送的电压输出到高电平电压输出端子，或者将外部电压提供为高电平电压。

公开(公告)号：US20110271157A1

公开(公告)日：2011-11-03

申请号：US12841070

申请日：2010-07-21

申请人： Kang Youl LEE ,  Mun Phil Park

发明人： Kang Youl LEE ,  Mun Phil Park

IPC分类号： G11C29/04 ,  G06F11/22

CPC分类号： G11C29/40

摘要： A test circuit of a semiconductor memory apparatus includes: a first fail detection unit configured to detect a fail of a memory cell group of a first memory block by combining a plurality of first test data signals outputted from the memory cell group of the first memory block; a second fail detection unit configured to detect a fail of a memory cell group of a second memory block by combining a plurality of second test data signals outputted from the memory cell group of the second memory block; a common fail detection unit configured to detect a fail of the memory cell groups of the first and second memory blocks by combining the plurality of first test data signals and the plurality of second test data signals; and a fail determination unit configured to output detection results of the first and second fail detection units or a detection result of the common is fail detection unit according to the detection results of the first and second fail detection units.

摘要翻译： 半导体存储装置的测试电路包括：第一故障检测单元，被配置为通过组合从第一存储块的存储单元组输出的多个第一测试数据信号来检测第一存储块的存储单元组的故障 ; 第二故障检测单元，被配置为通过组合从第二存储器块的存储单元组输出的多个第二测试数据信号来检测第二存储器块的存储单元组的故障; 公共故障检测单元，被配置为通过组合所述多个第一测试数据信号和所述多个第二测试数据信号来检测所述第一和第二存储器块的存储单元组的故障; 以及失败确定单元，被配置为根据第一和第二故障检测单元的检测结果，输出第一和第二故障检测单元的检测结果或公共检测结果为故障检测单元。

公开(公告)号：US20110002179A1

公开(公告)日：2011-01-06

申请号：US12614867

申请日：2009-11-09

申请人： Kwi-Dong Kim ,  Mun-Phil Park ,  Sung-Ho Kim

发明人： Kwi-Dong Kim ,  Mun-Phil Park ,  Sung-Ho Kim

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/10 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4096

摘要： A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks through a common data line in response to access information of the first and second memory banks.

摘要翻译： 半导体存储器件包括分别响应于第一和第二存储体选通信号而对第一和第二存储体执行数据写入操作的第一和第二写入驱动块，以及用于将数据传输到第一和第二写入的公共输入驱动块 驱动块通过公共数据线响应于第一和第二存储体的访问信息。

公开(公告)号：US20100309744A1

公开(公告)日：2010-12-09

申请号：US12494669

申请日：2009-06-30

申请人： Mun-Phil Park

发明人： Mun-Phil Park

IPC分类号： G11C8/18 ,  G11C8/00

CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C7/222

摘要： A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.

摘要翻译： 半导体器件包括：系统时钟输入单元，被配置为接收用于同步地址信号的输入时间和来自存储器控制器的命令信号的系统时钟;数据时钟输入单元，被配置为接收第一和第二数据时钟，用于使输入/ 来自存储器控制器的数据信号的输出时间，其中根据训练信息信号偏移第二数据时钟的相位，并且具有移位相位的第二数据时钟被输入到数据时钟输入单元，并且相位检测 单元，被配置为基于第一数据时钟的边缘来检测第二数据时钟的逻辑电平，并且生成训练信息信号，以根据检测到的逻辑电平将生成的信号发送到存储器控制器。

公开(公告)号：US07839705B2

公开(公告)日：2010-11-23

申请号：US12005505

申请日：2007-12-27

申请人： Mun-Phil Park

发明人： Mun-Phil Park

IPC分类号： G11C7/00

CPC分类号： G11C8/18

摘要： A semiconductor memory device has a timing margin for internal operations. The semiconductor memory device can activate an internal control signal for controlling an external address sooner than an internal control signal for controlling an external command to secure a sufficient time for data access. The semiconductor memory device includes a command decoding circuit configured to decode an external command to output an internal command signal for an internal operation corresponding to the external command, a control circuit configured to generate a strobe signal for controlling the internal operation in response to the internal command signal and an internal address signal by decoding an address signal received from outside such that the internal address signal activates sooner than the strobe signal, and a column decoding circuit configured to generate a data access signal when both the internal address signal and the strobe signal are activated.

摘要翻译： 半导体存储器件具有用于内部操作的定时裕度。 半导体存储器件可以激活用于控制外部地址的内部控制信号，而不是内部控制信号，用于控制外部命令以确保足够的时间进行数据访问。 半导体存储器件包括：命令解码电路，被配置为对外部命令进行解码以输出与外部命令相对应的内部操作的内部命令信号;控制电路，被配置为产生用于响应于内部的控制内部操作的选通信号 命令信号和内部地址信号，通过对从外部接收的地址信号进行解码，使得内部地址信号比选通信号更早地激活，列解码电路被配置为当内部地址信号和选通信号两者产生数据访问信号 被激活。

公开(公告)号：US07599230B2

公开(公告)日：2009-10-06

申请号：US11647367

申请日：2006-12-29

申请人： Mun-Phil Park

发明人： Mun-Phil Park

IPC分类号： G11C7/00

CPC分类号： G11C5/14 ,  G11C11/4074 ,  G11C11/4085

摘要： A semiconductor memory apparatus includes: a cell region having a plurality of unit cells each of which has a switching MOS transistor for transferring data. A peripheral circuit unit accesses data stored in the unit cell. A threshold voltage control unit controls the threshold voltage of the switching MOS transistor.

摘要翻译： 半导体存储装置包括：具有多个单元的单元区域，每个单位单元具有用于传送数据的开关MOS晶体管。 外围电路单元访问存储在单元中的数据。 阈值电压控制单元控制开关MOS晶体管的阈值电压。