公开(公告)号：US06505277B1

公开(公告)日：2003-01-07

申请号：US09344057

申请日：1999-06-25

Applicant: Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

Inventor： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC: G06F1200

CPC classification number: G06F12/0806 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F12/0811 ,  G06F12/0859

Abstract: A method for ordering the time of issue of a load instruction from a lower level (L2) intervening cache, interlinked by a system bus to a first L2 cache. The method comprises the steps of (i) appending a cycle of dependency (CoD) value to said load instruction, where the CoD value corresponds to a specified time, measured in cycles, on a synchronized timer (ST) at which the data is required by a downstream dependency, (ii) monitoring when a search of the first cache by said load instruction results in a miss, (iii) searching the load instruction at the second cache when the miss is detected, and (iv) providing the data requested by the load instruction from the intervening cache to a pipeline of a system resource of said first L2 cache at the specified time.

Abstract translation: 一种用于从由下一级（L2）中间缓存发出加载指令的时间的方法，该系统总线与第一L2高速缓存相互连接。 该方法包括以下步骤：（i）将附加循环（CoD）值附加到所述加载指令，其中CoD值对应于在需要数据的同步定时器（ST）上以周期测量的指定时间 通过下游依赖性，（ii）监视当所述加载指令对第一高速缓存的搜索导致错过时，（iii）在检测到未命中时搜索第二高速缓存上的加载指令，以及（iv）提供所请求的数据 通过在指定时间从中间缓存到所述第一L2高速缓存的系统资源的流水线的加载指令。

公开(公告)号：US06477613B1

公开(公告)日：2002-11-05

申请号：US09345302

申请日：1999-06-30

Applicant: Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  Jody B. Joyner ,  Jerry Don Lewis

Inventor： Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  Jody B. Joyner ,  Jerry Don Lewis

IPC: G06F1200

CPC classification number: G06F12/0811 ,  G06F12/0895 ,  G06F12/0897

Abstract: Following a cache miss by an operation, the address for the operation is transmitted on the bus coupling the cache to lower levels of the storage hierarchy. A portion of the address including the index field is transmitted during a first bus cycle, and may be employed to begin directory lookups in lower level storage devices before the address tag is received. The remainder of the address is transmitted during subsequent bus cycles, which should be in time for address tag comparisons with the congruence class elements. To allow multiple directory lookups to be occurring concurrently in a pipelined directory, a portion of multiple addresses for several data access operations, each portion including the index field for the respective address, may be transmitted during the first bus cycle or staged in consecutive bus cycles, with the remainders of each address—including the cache tags—transmitted during the subsequent bus cycles. This allows directory lookups utilizing the index fields to be processed concurrently within a lower level storage device for multiple operations, with the address tags being provided later, but still timely for tag comparisons at the end of the directory lookup. Where the lower level storage device operates at a higher frequency than the bus, overall latency is reduced and directory bandwidth is more efficiently utilized.

Abstract translation: 在操作的高速缓存未命中之后，操作的地址在将高速缓存耦合到存储层级的较低级别的总线上传输。 包括索引字段的地址的一部分在第一总线周期期间被发送，并且可以用于在接收到地址标签之前开始下级存储设备中的目录查找。 在随后的总线周期期间传送地址的其余部分，这些时间应与地址标签与同余类元素进行比较。 为了允许在流水线目录中同时发生多个目录查找，可以在第一个总线周期期间发送多个数据访问操作的多个地址的一部分，每个部分包括相应地址的索引字段，或者在连续的总线周期中分段 ，每个地址的剩余部分，包括在后续总线周期期间发送的缓存标签。 这允许使用索引字段的目录查找在较低级存储设备中同时处理以用于多个操作，其中地址标签稍后提供，但是在目录查找结束时仍然适合于标签比较。 在较低级存储设备以比总线更高的频率工作的地方，总体延迟降低，目录带宽更有效地利用。

公开(公告)号：US06473833B1

公开(公告)日：2002-10-29

申请号：US09364570

申请日：1999-07-30

Applicant: Ravi Kumar Arimilli ,  Leo James Clark ,  James Stephen Fields, Jr. ,  Lakshminarayana Baba Arimilli

Inventor： Ravi Kumar Arimilli ,  Leo James Clark ,  James Stephen Fields, Jr. ,  Lakshminarayana Baba Arimilli

IPC: G06F1200

CPC classification number: G06F12/0897

Abstract: A method of operating a multi-level memory hierarchy of a computer system and an apparatus embodying the method, wherein multiple levels of storage subsystems are used to improve the performance of the computer system, each next higher level generally having a faster access time, but a smaller amount of storage. Values within a level are indexed by a directory that provides an indexing of information relating the values in that level to the next lower level. In a preferred embodiment of the invention, the directories for the various levels of storage are contained within the next higher level, providing a faster access to the directory information. Cache memories used as the highest levels of storage, and one or more sets are allocated out of that cache memory for containing a directory of the next lower level of storage. An address comparator which is used to compare entries in a directory to address values is directly coupled to the set or sets used for the directory, reducing the time needed to compare addresses in determining whether an address is present in the cache.

Abstract translation: 一种操作计算机系统的多级存储器层级的方法和体现该方法的装置，其中使用多级存储子系统来提高计算机系统的性能，每个下一级别通常具有更快的访问时间，但是 更少的存储空间。 级别中的值由一个目录索引，该目录提供与该级别中的值相关联的信息与下一级别的索引。 在本发明的优选实施例中，用于各种级别的存储的目录被包含在下一较高级别内，从而提供对目录信息的更快访问。 高速缓冲存储器被用作最高级别的存储器，并且从该高速缓存存储器中分配一个或多个集合，用于包含下一较低级存储的目录。 用于将目录中的条目与地址值进行比较的地址比较器直接耦合到用于目录的集合或集合，减少了在确定地址是否存在于高速缓存中时比较地址所需的时间。

公开(公告)号：US06460118B1

公开(公告)日：2002-10-01

申请号：US09339410

申请日：1999-06-24

Applicant: Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie

Inventor： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie

IPC: C06F1200

CPC classification number: G06F12/0864 ,  G06F12/1054

Abstract: A set-associative cache memory having incremental access latencies among sets is disclosed. The cache memory has multiple congruence classes of cache lines. Each congruence class includes a number of sets organized in a set-associative manner. In accordance with a preferred embodiment of the present invention, the cache memory further includes a means for accessing each of the sets with an access time dependent on a relative location of each of the sets such that access latency varies incrementally among sets.

Abstract translation: 公开了一种在集合中具有增量接入延迟的集合关联高速缓冲存储器。 高速缓存存储器具有多个一致的缓存行类。 每个同余类包括以组合方式组织的多个集合。 根据本发明的优选实施例，高速缓存存储器还包括用于以取决于每个集合的相对位置的访问时间来访问每个集合的装置，使得访问延迟在集合之间递增地变化。

公开(公告)号：US06460117B1

公开(公告)日：2002-10-01

申请号：US09339409

申请日：1999-06-24

Applicant: Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie

Inventor： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie

IPC: G06F1200

CPC classification number: G06F12/0893 ,  G06F12/0864 ,  G06F12/123

Abstract: A set-associative cache memory having a mechanism for migrating a most recently used set is disclosed. The cache memory has multiple congruence classes of cache lines. Each congruence class includes a number of sets organized in a set-associative manner. The cache memory further includes a migration means for directing the information from a cache “hit” to a predetermined set of the cache memory.

Abstract translation: 公开了具有用于迁移最近使用的集合的机制的集合关联缓存存储器。 高速缓存存储器具有多个一致的缓存行类。 每个同余类包括以组合方式组织的多个集合。 高速缓冲存储器还包括用于将信息从高速缓存“命中”引导到高速缓冲存储器的预定集合的迁移装置。

公开(公告)号：US06442653B1

公开(公告)日：2002-08-27

申请号：US09339403

申请日：1999-06-24

Applicant: Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai

Inventor： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai

IPC: G06F1200

CPC classification number: G06F12/0815 ,  G06F12/127 ,  G06F2212/2542

Abstract: A data processing system includes a processing unit, a distributed memory including a local memory and a remote memory having differing access latencies, and a cache coupled to the processing unit and to the distributed memory. The cache includes data storage and a plurality of latency indicators that each indicate an access latency to the distributed memory for associated data stored in the data storage. As a result, transactions related to cached data can be efficiently routed and addressed and efficient victim selection and deallocation policies can be implemented in the cache.

Abstract translation: 数据处理系统包括处理单元，包括本地存储器的分布式存储器和具有不同访问延迟的远程存储器，以及耦合到处理单元和分布式存储器的高速缓存。 高速缓存包括数据存储器和多个等待时间指示器，每个等待时间指示器指示分配的存储器对存储在数据存储器中的相关数据的访问等待时间。 因此，可以有效地路由和寻址与缓存数据相关的事务，并且可以在缓存中实现有效的牺牲者选择和释放策略。

公开(公告)号：US06434670B1

公开(公告)日：2002-08-13

申请号：US09435948

申请日：1999-11-09

Applicant: Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie

Inventor： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie

IPC: G06F1200

CPC classification number: G06F12/0864 ,  G06F12/123

Abstract: A method and apparatus for efficiently managing caches with non-power-of-two congruence classes allows for increasing the number of congruence classes in a cache when not enough area is available to double the cache size. One or more congruence classes within the cache have their associative sets split so that a number of congruence classes are created with reduced associativity. The management method and apparatus allow access to the congruence classes without introducing any additional cycles of delay or complex logic.

Abstract translation: 一种用于非有效二等度类的高效管理高速缓存的方法和装置允许当没有足够的区域可用于使高速缓存大小加倍时，增加高速缓存中的同余类的数量。 高速缓存中的一个或多个同余类别将其关联集合拆分，从而创建具有降低的关联性的多个同余类。 管理方法和装置允许访问一致类，而不引入任何额外的延迟周期或复杂的逻辑。

公开(公告)号：US06434667B1

公开(公告)日：2002-08-13

申请号：US09340075

申请日：1999-06-25

Applicant: Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie

Inventor： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie

IPC: G06F1200

CPC classification number: G06F12/0811 ,  G06F12/0859 ,  G06F12/0888

Abstract: A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (L1) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information). L2 control of the L1 directory also allows certain snoop requests to be resolved without waiting for L1 acknowledgement. The invention can be applied to, e.g., instruction, operand data and translation caches.

Abstract translation: 一种改进计算机系统的存储器访问的方法，通过将请求发送到较低级别的存储子系统以及由请求处理器对与请求的信息的预期用途有关的关联信息而不使用高级别的负载队列来进行发送。 将所请求的信息与相关联的使用信息一起返回到处理器允许立即放置信息而不使用重新加载缓冲器。 使用与缓存负载总线分离（并具有较小粒度）的寄存器负载总线返回信息。 然后可能不精确地重新加载上级（L1）高速缓存（高级缓存也可以不精确地用存储指令重新加载）。 低级（L​​2）缓存可以监视L1和L2高速缓存活动，其可用于在L1高速缓存中选择受害者缓存块（基于附加的L2信息），或者选择L2缓存中的受害缓存块（ 基于附加的L1信息）。 L1目录的L2控制也允许解决某些侦听请求，而无需等待L1确认。 本发明可以应用于例如指令，操作数数据和翻译高速缓存。

公开(公告)号：US06421763B1

公开(公告)日：2002-07-16

申请号：US09345642

申请日：1999-06-30

Applicant: Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  James Stephen Fields, Jr.

Inventor： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  James Stephen Fields, Jr.

IPC: G06F1208

CPC classification number: G06F12/0862 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3885 ,  G06F12/0897 ,  G06F2212/6028

Abstract: A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster). If another prefetch value is requested from the memory hierarchy, and it is determined that a prefetch limit of cache usage has been met by the cache, then a cache line in the cache containing one of the earlier prefetch values is allocated for receiving the other prefetch value. The prefetch limit of cache usage may be established with a maximum number of sets in a congruence class usable by the requesting processing unit. A flag in a directory of the cache may be set to indicate that the prefetch value was retrieved as the result of a prefetch operation. In the implementation wherein the cache is a multi-level cache, a second flag in the cache directory may be set to indicate that the prefetch value has been sourced to an upstream cache. A cache line containing prefetch data can be automatically invalidated after a preset amount of time has passed since the prefetch value was requested.

Abstract translation: 一种操作计算机系统的处理单元的方法，通过从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。 本发明适用于作为操作数数据或指令的值。 在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别 存储子系统，并用预取请求发送将预取值加载到处理单元的较低级缓存中的指示。 本发明可以有利地将每个预取请求与相关联的处理器流的流ID或请求处理单元的处理器ID相关联（后一特征对于由处理单元簇共享的高速缓存特别有用）。 如果从存储器层次结构请求另一个预取值，并且确定高速缓存的高速缓存使用的预取限制已经被高速缓存满足，则分配包含较早预取值之一的高速缓存行中的高速缓存行用于接收另一个预取 值。 高速缓存使用的预取限制可以由请求处理单元可用的同余类中的最大数量的集合来建立。 高速缓存目录中的标志可以被设置为指示作为预取操作的结果检索预取值。 在其中缓存是多级高速缓存的实现中，高速缓存目录中的第二标志可以被设置为指示预取值已经被提供给上游高速缓存。 包含预取数据的缓存行可以在从请求预取值开始经过预设的时间后自动失效。

公开(公告)号：US06421761B1

公开(公告)日：2002-07-16

申请号：US09435950

申请日：1999-11-09

Applicant: Ravi Kumar Arimilli ,  Bryan Ronald Hunt ,  William John Starke

Inventor： Ravi Kumar Arimilli ,  Bryan Ronald Hunt ,  William John Starke

IPC: G06F1200

CPC classification number: G06F12/0848

Abstract: A partitioned cache and management method for selectively caching data by type improves the efficiency of a cache memory by partitioning congruence class sets for storage of particular data types such as operating system routines and data used by those routines. By placing values for associated applications into different partitions in the cache, values can be kept simultaneously available in cache with no interference that would cause deallocation of some values in favor of newly loaded values. Additionally, placing data from unrelated applications in the same partition can be performed to allow the cache to rollover values that are not needed simultaneously.

Abstract translation: 用于按类型选择性地缓存数据的分区高速缓存和管理方法通过划分一致类集合来存储特定数据类型（例如操作系统例程和这些例程所使用的数据）来提高高速缓冲存储器的效率。 通过将相关应用程序的值放置在缓存中的不同分区中，可以在缓存中保持同时可用的值，而不会造成任何干扰，从而导致某些值的释放，从而有利于新加载的值。 另外，可以执行将来自不相关的应用程序的数据放在同一分区中，以允许高速缓存翻转不同时间的值。