公开(公告)号：US20060120195A1

公开(公告)日：2006-06-08

申请号：US10908534

申请日：2005-05-16

申请人： Sang Hee Kang

发明人： Sang Hee Kang

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C7/22 ,  G11C8/18

摘要： A voltage generation control circuit of a semiconductor memory device and method thereof are provided. A period tD, which is delayed for a given time after an internal row active time (tRAS) is secured since an active command is input, is set as an active operating period. An internal latency period, a burst length period and a latency delay period tDLT are set as a read/write operating period after a read/write command is input. A period tDRP delayed for a given time after a precharge command is input is set as a precharge operating period. In this state, a voltage generator is controlled to generate an active voltage only in the operating periods.

摘要翻译： 提供半导体存储器件的电压产生控制电路及其方法。 在输入有效命令之后，在内部行活动时间（tRAS）被确定之后延迟给定时间的周期tD被设置为活动操作周期。 在输入读/写命令之后，将内部等待时间周期，突发长度周期和等待时间延迟周期tDLT设置为读/写操作周期。 将预充电命令输入后的给定时间延迟的时段tDRP设定为预充电动作期间。 在这种状态下，电压发生器被控制以仅在操作周期中产生有效电压。

公开(公告)号：US20050162945A1

公开(公告)日：2005-07-28

申请号：US11015419

申请日：2004-12-20

申请人： Sang-Hee Kang ,  Sung-Joo Ha ,  Ho-Youb Cho

发明人： Sang-Hee Kang ,  Sung-Joo Ha ,  Ho-Youb Cho

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C29/808

摘要： A semiconductor memory device, including: a plurality of banks each of which includes a plurality of memory cells, a plurality of redundancy memory cells for replacing a defective memory cell and a repair circuit, having a plurality of fuse sets, for substituting an address to thereby access the redundancy memory cell instead of the defective memory cell; and a common repair circuit, having a plurality of fuse sets, for substituting the address in order to replace the defective memory cell with the redundancy memory cell included in any of the plurality of banks.

摘要翻译： 一种半导体存储器件，包括：多个存储体，每个存储体包括多个存储单元，用于替换有缺陷存储单元的多个冗余存储单元和具有多个熔丝组的修复电路，用于将地址替换为 从而访问冗余存储单元而不是有缺陷的存储单元; 以及具有多个熔丝组的通用修复电路，用于代替所述地址以便用所述多个存储体中的任一个中包含的所述冗余存储单元替换所述有缺陷的存储单元。

公开(公告)号：US06879197B2

公开(公告)日：2005-04-12

申请号：US10699722

申请日：2003-11-03

申请人： Chang Seok Kang ,  Sang Hee Kang

发明人： Chang Seok Kang ,  Sang Hee Kang

IPC分类号： G11C11/4091 ,  G11C7/06 ,  H03F3/45 ,  H03K3/02

CPC分类号： G11C7/06 ,  G11C2207/065

摘要： The apparatus for generating a driving voltage for a sense amplifier has at least voltage output means, and first and second core voltage step-up means. The voltage output means outputs a voltage for driving the sense amplifier to a node. Each of the first and second core voltage step-up means are connected between a power supply and the node. The first and second core voltage step-up means are turned on in sequence to elevate the voltage level of the node connected with the sense amplifier up to the level of the power supply. This enhances the performance of the sense amplifier as well as the execute detection amplification in a short time period. The first and second core voltage step-up means are turned on in sequence to elevate the core voltage as the driving voltage, reducing the power noise. Each core voltage step-up driver may be installed in each bank to reduce power consumption.

摘要翻译： 用于产生用于感测放大器的驱动电压的装置至少具有电压输出装置，以及第一和第二电芯升压装置。 电压输出装置将用于驱动读出放大器的电压输出到节点。 第一和第二核心电压升压装置中的每一个连接在电源和节点之间。 第一和第二核心电压升压装置依次导通，以将与感测放大器连接的节点的电压电平提升到电源的电平。 这增强了读出放大器的性能以及在短时间内执行检测放大。 第一和第二核心电压升压装置按顺序导通，以提高核心电压作为驱动电压，从而降低功率噪声。 每个核心电压升压驱动器可以安装在每个存储体中以降低功耗。

公开(公告)号：US07602659B2

公开(公告)日：2009-10-13

申请号：US10965550

申请日：2004-10-14

申请人： Sang Hee Kang

发明人： Sang Hee Kang

IPC分类号： G11C7/00

CPC分类号： G11C29/808

摘要： A memory device sharing a fail-repairing part is disclosed. The memory device has a plurality of banks that share a fuse and control unit for repairing a row fail or column fail in memory cell arrays in the respective banks. The memory device has reduced size and improved repair efficiency.

摘要翻译： 公开了共享故障修复部件的存储器件。 存储器件具有多个存储体，其共享用于修复各个存储体中的存储单元阵列中的行故障或列失败的熔丝和控制单元。 存储器件具有减小的尺寸并提高修复效率。

公开(公告)号：US07450455B2

公开(公告)日：2008-11-11

申请号：US11529570

申请日：2006-09-29

申请人： Sang-Hee Kang ,  Hi-Hyun Han ,  Ho-Youb Cho

发明人： Sang-Hee Kang ,  Hi-Hyun Han ,  Ho-Youb Cho

IPC分类号： G11C11/00

CPC分类号： G11C7/08 ,  G11C7/02 ,  G11C7/065 ,  G11C11/4091 ,  G11C2207/065

摘要： A semiconductor memory device prevents deterioration of refresh operation caused by sensing noise and a driving method thereof. First pull-down and second pull-down voltages which are different from each other are as a pull-down voltage of a bit line sense amplifier. The first and the second pull-down voltages are used in different driving periods to protect data from noises caused by another memory bank. A driving period can be separated into an initial sensing period, wherein large currents are consumed and significant noise is generated, and a subsequent stable period. The driving period can be separated into a pre-precharge period and a post-precharge period.

摘要翻译： 半导体存储器件防止由感测噪声引起的刷新操作的劣化及其驱动方法。 彼此不同的第一下拉和第二下拉电压作为位线读出放大器的下拉电压。 第一和第二下拉电压用于不同的驱动周期以保护数据免受另一个存储体引起的噪声。 驱动周期可以分为初始感测周期，其中消耗大电流并产生显着的噪声，以及随后的稳定周期。 驱动周期可以分为预充电期和预充电期。

公开(公告)号：US20080150622A1

公开(公告)日：2008-06-26

申请号：US12073115

申请日：2008-02-29

申请人： Sang-Hee Kang

发明人： Sang-Hee Kang

IPC分类号： G05F5/00

CPC分类号： G11C5/145

摘要： A semiconductor integrated circuit comprising: a first voltage generator configured to generate a first voltage in response to activation of a first enable signal, wherein the first enable signal is generated by detecting a level of the first voltage; and a second voltage generator configured to generate a second voltage in response to activation of at least one of the first enable signal and a second enable signal, wherein the second enable signal is generated by detecting a level of the second voltage.

摘要翻译： 一种半导体集成电路，包括：第一电压发生器，被配置为响应于第一使能信号的激活而产生第一电压，其中通过检测第一电压的电平来产生第一使能信号; 以及第二电压发生器，被配置为响应于所述第一使能信号和第二使能信号中的至少一个的激活而产生第二电压，其中通过检测所述第二电压的电平来产生所述第二使能信号。

公开(公告)号：US07379378B2

公开(公告)日：2008-05-27

申请号：US11712466

申请日：2007-03-01

申请人： Hi-Hyun Han ,  Sang-Hee Kang

发明人： Hi-Hyun Han ,  Sang-Hee Kang

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/08 ,  G11C11/4091

摘要： A bit line over driving control signal generator generates an over driving control signal in response to an over driving signal. The over driving signal is generated in response to an active command. The bit line over driving control signal generator for use in a semiconductor memory device includes a delaying unit for delaying an over driving signal generated in response to an active command to thereby output a delayed over driving signal, a controlling unit for determining whether the delayed over driving signal is outputted without any modification or outputted with being disabled in response to the over driving signal, a read command, and a precharge command, and a pulse width adding unit for adding a predetermined pulse width of the delayed over driving signal to the over driving signal to thereby output a bit line over driving control signal.

摘要翻译： 驱动控制信号发生器的位线响应过驱动信号产生过驱动控制信号。 响应于主动命令产生过驱动信号。 用于半导体存储装置的位线驱动控制信号发生器包括：延迟单元，用于延迟响应于有效命令产生的过驱动信号，从而输出延迟驱动信号;控制单元，用于确定是否延迟 驱动信号被输出而没有任何修改或响应于过驱动信号，读命令和预充电命令而被禁用输出，以及脉冲宽度相加单元，用于将延迟过驱动信号的预定脉冲宽度加到上 驱动信号，从而在驱动控制信号上输出位线。

公开(公告)号：US07196965B2

公开(公告)日：2007-03-27

申请号：US11191008

申请日：2005-07-28

申请人： Hi-Hyun Han ,  Sang-Hee Kang

发明人： Hi-Hyun Han ,  Sang-Hee Kang

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/08 ,  G11C11/4091

摘要： A bit line over driving control signal generator generates an over driving control signal in response to an over driving signal. The over driving signal is generated in response to an active command. The bit line over driving control signal generator for use in a semiconductor memory device includes a delaying unit for delaying an over driving signal generated in response to an active command to thereby output a delayed over driving signal, a controlling unit for determining whether the delayed over driving signal is outputted without any modification or outputted with being disabled in response to the over driving signal, a read command, and a precharge command, and a pulse width adding unit for adding a predetermined pulse width of the delayed over driving signal to the over driving signal to thereby output a bit line over driving control signal.

公开(公告)号：US20060245279A1

公开(公告)日：2006-11-02

申请号：US11262105

申请日：2005-10-28

申请人： Sang-Hee Kang

发明人： Sang-Hee Kang

IPC分类号： G11C29/00

CPC分类号： G11C29/838 ,  G11C29/787

摘要： A redundancy circuit in a semiconductor memory device comprises a fuse set controller configured to output a redundancy enable signal enabled according to applied address signals; a redundant selector; a spare redundant selector; and a spare fuse controller configured to be controlled by the redundancy enable signal, and to output a selection control signal that selects at least one of the redundant selector and the spare redundant selector in accordance with an internal fuse option.

摘要翻译： 半导体存储器件中的冗余电路包括：熔丝组控制器，配置为输出根据所施加的地址信号使能的冗余使能信号; 冗余选择器 备用冗余选择器; 以及备用熔丝控制器，其被配置为由所述冗余启用信号控制，并且输出选择控制信号，所述选择控制信号根据内部熔丝选项选择所述冗余选择器和备用冗余选择器中的至少一个。

公开(公告)号：US20050094344A1

公开(公告)日：2005-05-05

申请号：US11010747

申请日：2004-12-13

申请人： Sang Hee Kang ,  Dong Gyu Lee ,  Seung Hyun ,  Yong Kang

发明人： Sang Hee Kang ,  Dong Gyu Lee ,  Seung Hyun ,  Yong Kang

IPC分类号： G01R15/18 ,  H02H1/04 ,  H02M3/335

CPC分类号： H02H1/046 ,  G01R15/183 ,  H02M2001/0009

摘要： Disclosed herein is a method of compensating for the distorted secondary current of a current transformer. The method includes steps (a), (b) and (c). At step (a), the saturated section of the current transformer is detected. At step (b), fault current generated during a fault in a power system is represented using an AutoRegressive (AR) model, with the fault current being assumed to be a combination of a Direct Current (DC) offset component, a fundamental wave component and a harmonic component. At step (c), normal secondary current during the saturation of the current transformer is estimated using a plurality of pieces of sampled secondary current data, based on the estimated coefficient of the AR model.

摘要翻译： 本文公开了一种补偿电流互感器的失真次级电流的方法。 该方法包括步骤（a），（b）和（c）。 在步骤（a）中，检测电流互感器的饱和部分。 在步骤（b）中，使用自动反馈（AR）模型来表示电力系统故障期间产生的故障电流，故障电流假定为直流（DC）偏移分量，基波分量 和谐波分量。 在步骤（c）中，基于AR模型的估计系数，使用多个采样次级电流数据估计电流互感器饱和期间的正常次级电流。