摘要:
Disclosed herein is a Fourier transform-based phasor estimation method and apparatus capable of eliminating the influence of exponentially decaying DC offsets. According to a Fourier transform-based phasor estimation method according to an embodiment of the present invention, an input signal is sampled, and samples of one-cycle data of the input signal are separated into at least two sample groups. A Discrete Fourier Transform (DFT) is performed on each of the sample groups. A DC offset included in the input signal is calculated on a basis of results of the DFT on each of the sample groups, and an error caused by the DC offset is calculated using the calculated DC offset. A phasor of a fundamental frequency component included in the input signal is estimated by eliminating the calculated error, caused by the DC offset, from the results of the DFT on the input signal.
摘要:
A redundancy circuit in a semiconductor memory device comprises a fuse set controller configured to output a redundancy enable signal enabled according to applied address signals; a redundant selector; a spare redundant selector; and a spare fuse controller configured to be controlled by the redundancy enable signal, and to output a selection control signal that selects at least one of the redundant selector and the spare redundant selector in accordance with an internal fuse option.
摘要:
Disclosed herein are an internal voltage generation control circuit and an internal voltage generation circuit using the same. The internal voltage generation control circuit comprises a row active controller for enabling a first internal voltage generation control signal when a row active signal is enabled upon input of an active command and then disabling the first internal voltage generation control signal after the lapse of a first predetermined delay time if an RAS activation guarantee signal is enabled at a RAS active time after the first internal voltage generation control signal is enabled, an input/output controller for enabling a second internal voltage generation control signal when the row active signal and at least one of a data input signal and a data output signal are enabled and then disabling the second internal voltage generation control signal after the lapse of a second predetermined delay time if a row precharge signal is enabled or if the data input signal and data output signal are disabled, and a row precharge controller for enabling a third internal voltage generation control signal for a third predetermined delay time if the row precharge signal is enabled.
摘要:
The present invention is related to a negative voltage generating circuit for reliably providing the semiconductor integrated circuit (IC) with a negative voltage. An electric charge pumping device generates a negative voltage by pumping an electric charge to a predetermined level supplied to one of a first node and a second node. A controlling device provides first and second pumping clock signal being clocked alternately every predetermined interval in response to a level of the negative voltage. A pumping controller controls an amount of electric charge supplied to the first node and the second node in response to the first and second pumping clock signals. Further, a reset controller resets the first node and the second node of the electric charge pumping means as the level of the negative voltage when the first and second pumping clock signals are inactivated.
摘要:
An internal voltage generation control circuit and an internal voltage generation circuit using the same are provided. The internal voltage generation control circuit comprises first to n-th latches and a logic unit. The first latch receives, as an input signal, a column active pulse signal generated after a read/write command is input, and latches state information of the column active pulse signal, received when a clock signal is enabled, during a predetermined time, and then outputs the latched information. A k-th latch (2≦k≦n) receives an output signal of a k-1-th latch, and latches state information of the output signal of the k-1-th latch, received when the clock signal is enabled, during a predetermined time, and then outputs the latched information. The logic unit performs a logical operation between the column active pulse signal and output signals of the n latches and outputs an internal voltage generation control signal.
摘要:
A redundancy circuit in a semiconductor memory device comprises a fuse set controller configured to output a redundancy enable signal enabled according to applied address signals; a redundant selector; a spare redundant selector; and a spare fuse controller configured to be controlled by the redundancy enable signal, and to output a selection control signal that selects at least one of the redundant selector and the spare redundant selector in accordance with an internal fuse option.
摘要:
A shared delay circuit of a semiconductor device can share a plurality of delay elements having the same function by integrating the delay elements. The shared delay circuit includes an input signal conversion unit for converting a plurality of input signals into a plurality of pulse signals, a delay unit for delaying the pulse signals outputted from the input signal conversion unit for a predetermined time to output the delayed pulse signal, and a switch and output control unit for receiving the pulse signals outputted from the input signal conversion unit and the delayed pulse signals delayed for the predetermined time through the delay unit, and outputting the delayed pulse signals in the same form as the input signals inputted to the input signal conversion unit. According to the shared delay circuit, the repeated arrangement of circuits having the same function can be avoided by sharing the delay circuits in the semiconductor device and thus the installation area of the delay circuits can be reduced.
摘要:
Disclosed is a relaying method for protecting a transformer by using a difference of current. A decision function, related to the rate of change of a primary current, a secondary current, or a differential current, is used for determining whether a detected abnormal current is due to the inrush or internal fault.
摘要:
Row access information transfer devices and methods are disclosed which use an internal wiring of a memory cell array to transfer information to a column fuse box array. The disclosed techniques and structures can increase the efficiency of a circuit by transferring sense amplifier and wordline control signals relating to a specific row block corresponding to an inputted row address to a column fuse box array using wiring within the cell array, when the row block is accessed in DRAM.
摘要:
An internal voltage generating circuit and a semiconductor memory device including the internal voltage generating circuit are disclosed. The internal voltage generating circuit includes a first voltage generating circuit, a second voltage generating circuit, and a third voltage generating circuit. The first voltage generating circuit stabilizes a first external supply voltage to generate a first internal voltage. The second voltage generating circuit stabilizes the first external supply voltage and a second external supply voltage to generate a second internal voltage having a voltage level higher than the first internal voltage. The third voltage generating circuit stabilizes the second internal voltage to generate a third internal voltage having a voltage level lower than the second internal voltage. Accordingly, the semiconductor memory device may be insensitive to a change in an external supply voltage and have small power consumption.