公开(公告)号：US20120181532A1

公开(公告)日：2012-07-19

申请号：US13101983

申请日：2011-05-05

Applicant: Chin-Wen LIN ,  Chuan-I HUANG ,  Chung-Chin HUANG ,  Ted Hong SHINN

Inventor： Chin-Wen LIN ,  Chuan-I HUANG ,  Chung-Chin HUANG ,  Ted Hong SHINN

IPC: H01L29/786 ,  H01L21/36

CPC classification number: H01L23/3192 ,  H01L23/3171 ,  H01L29/78603 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal oxide semiconductor structure and a production method thereof, the structure including: a substrate; a gate electrode, deposited on the substrate; a gate insulation layer, deposited over the gate electrode and the substrate; an IGZO layer, deposited on the gate insulation layer and functioning as a channel; a source electrode, deposited on the gate insulation layer and being at one side of the IGZO layer; a drain electrode, deposited on the gate insulation layer and being at another side of the IGZO layer; a first passivation layer, deposited over the source electrode, the IGZO layer, and the drain electrode; a second passivation layer, deposited over the first passivation layer; and an opaque resin layer, deposited over the source electrode, the second passivation layer, and the drain electrode.

Abstract translation: 一种金属氧化物半导体结构及其制造方法，其结构包括：基板; 沉积在基板上的栅电极; 栅极绝缘层，沉积在栅电极和衬底上; IGZO层，沉积在栅极绝缘层上并用作沟道; 源电极，淀积在栅极绝缘层上并位于IGZO层的一侧; 漏电极，沉积在栅极绝缘层上并位于IGZO层的另一侧; 沉积在源电极，IGZO层和漏极上的第一钝化层; 沉积在所述第一钝化层上的第二钝化层; 以及沉积在源电极，第二钝化层和漏电极上的不透明树脂层。

公开(公告)号：US20120105419A1

公开(公告)日：2012-05-03

申请号：US12913804

申请日：2010-10-28

Applicant: Wen-Lin Yang ,  Shih-Yu Wen

Inventor： Wen-Lin Yang ,  Shih-Yu Wen

IPC: G09G3/36 ,  G06F3/038

CPC classification number: G09G3/3614 ,  G09G3/3655 ,  G09G3/3688 ,  G09G2310/0291 ,  G09G2330/02 ,  G09G2330/021

Abstract: A driving circuit with reduced power consumption and a liquid crystal display using the same. The driving circuit includes at least a power circuit, a source driver and a VCOM driver. The power circuit is coupled to a power supply to receive a power signal to generate a positive supply voltage and an inverted power signal. The source driver includes a first source operational amplifier. The first source operational amplifier is powered by the positive supply voltage and a power ground, to couple a positive polarity display voltage to a first terminal of a first display capacitor of a pixel array. The VCOM driver includes a VCOM operational amplifier. The VCOM operational amplifier provides a second terminal of the first display capacitor with a VCOM voltage, and a negative power terminal of the VCOM operational amplifier is coupled to the inverted power signal.

Abstract translation: 具有降低功耗的驱动电路和使用该驱动电路的液晶显示器。 驱动电路至少包括电源电路，源极驱动器和VCOM驱动器。 电源电路耦合到电源以接收电力信号以产生正电源电压和反相功率信号。 源极驱动器包括第一源极运算放大器。 第一源运算放大器由正电源电压和电源地供电，以将正极性显示电压耦合到像素阵列的第一显示电容器的第一端子。 VCOM驱动器包括一个VCOM运算放大器。 VCOM运算放大器提供具有VCOM电压的第一显示电容器的第二端子，并且VCOM运算放大器的负电源端子耦合到反相功率信号。

公开(公告)号：US20120083135A1

公开(公告)日：2012-04-05

申请号：US12898037

申请日：2010-10-05

Applicant: Chun Hsiung TSAI ,  Chii-Ming WU ,  Da-Wen LIN

Inventor： Chun Hsiung TSAI ,  Chii-Ming WU ,  Da-Wen LIN

IPC: H01L21/26

CPC classification number: H01L21/324 ,  H01L21/26513 ,  H01L21/67248

Abstract: Rapid thermal annealing methods and systems for annealing patterned substrates with minimal pattern effect on substrate temperature non-uniformity are provided. The rapid thermal annealing system includes a front-side heating source and a backside heating source. The backside heating source of the rapid thermal annealing system supplies a dominant amount of heat to bring the substrate temperature to the peak annealing temperature. The front-side heating source contributes to heat up the environment near the front-side of the substrate to a temperature lower than about 100° C. to about 200° C. less than the peak annealing temperature. The asymmetric front-side and backside heating for rapid thermal annealing reduce or eliminate pattern effect and improve WIW and WID device performance uniformity.

Abstract translation: 提供了用于退火图案化衬底的快速热退火方法和系统，对衬底温度的不均匀性具有最小的图案效应。 快速热退火系统包括前侧加热源和背面加热源。 快速热退火系统的背面加热源提供显着的热量以使衬底温度达到峰值退火温度。 前侧加热源有助于将基板前侧附近的环境加热到低于峰值退火温度的约100℃至约200℃的温度。 用于快速热退火的不对称前侧和后侧加热减少或消除图案效应，并提高WIW和WID器件的性能均匀性。

公开(公告)号：US08142880B2

公开(公告)日：2012-03-27

申请号：US12634800

申请日：2009-12-10

Applicant: Ben-Ding Tsao ,  Wen-Lin Xiong ,  Qi-Quan Yan ,  Yue-Jun He ,  Man-Xiang Duan ,  San-Yuan Wen

Inventor： Ben-Ding Tsao ,  Wen-Lin Xiong ,  Qi-Quan Yan ,  Yue-Jun He ,  Man-Xiang Duan ,  San-Yuan Wen

IPC: B32B3/00 ,  B32B3/28 ,  B32B3/30 ,  H05K5/00 ,  H05K7/00

CPC classification number: B29C45/1418 ,  B29C45/372 ,  B32B27/00 ,  B32B27/36 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/24612

Abstract: A housing for an electronic device is disclosed, the housing comprises a base layer and a transparent film layer overlapped in the base layer, the film layer includes an inner surface abutting the base layer and an outer surface having ridges protruding thereform. The housing is formed by injection molding a molten plastic material over the transparent film layer, the ridges are formed on the transparent film layer by the molten plastic pressing the transparent film layer in injection molding. It is also disclosed a mold for making the housing and a method to make the housing.

Abstract translation: 公开了一种用于电子设备的壳体，该壳体包括基底层和与该基底层重叠的透明薄膜层，该薄膜层包括邻接基底层的内表面和具有突出突起的脊的外表面。 通过在透明膜层上注射熔融塑料材料形成壳体，通过在注射成型中压制透明膜层的熔融塑料在透明膜层上形成脊。 还公开了一种用于制造壳体的模具和制造壳体的方法。

公开(公告)号：US20120018848A1

公开(公告)日：2012-01-26

申请号：US12840830

申请日：2010-07-21

Applicant: Yu-Lien Huang ,  Mao-Rong Yeh ,  Chun Hsiung Tsai ,  Tsung-Hung Lee ,  Da-Wen Lin ,  Tsz-Mei Kwok

Inventor： Yu-Lien Huang ,  Mao-Rong Yeh ,  Chun Hsiung Tsai ,  Tsung-Hung Lee ,  Da-Wen Lin ,  Tsz-Mei Kwok

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/36

CPC classification number: H01L21/823807 ,  H01L21/2236 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7848

Abstract: The present disclosure provides a high surface dopant concentration semiconductor device and method of fabricating. In an embodiment, a method of forming the semiconductor device includes providing a substrate, forming a doped region in the substrate, forming a stressing layer over the doped region, performing a boron (B) doping implant to the stressing layer, annealing the B doping implant, and after annealing the B doping implant, forming a silicide layer over the stressing layer.

Abstract translation: 本公开提供了高表面掺杂浓度的半导体器件及其制造方法。 在一个实施例中，形成半导体器件的方法包括提供衬底，在衬底中形成掺杂区域，在掺杂区域上形成应力层，对应力层执行硼（B）掺杂注入，退火B掺杂 并且在B掺杂注入退火之后，在应力层上形成硅化物层。

公开(公告)号：US20110248351A1

公开(公告)日：2011-10-13

申请号：US12757465

申请日：2010-04-09

Applicant: Chung-Yu Chiang ,  Da-Wen Lin ,  Shyh-Wei Wang

Inventor： Chung-Yu Chiang ,  Da-Wen Lin ,  Shyh-Wei Wang

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/0847 ,  H01L21/266 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/6659 ,  H01L29/7833

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. An exemplary method includes providing a substrate; forming a first gate over the substrate for a first device having a first threshold voltage characteristic, the first gate including a first material having a first-type work function; forming a second gate over the substrate for a second device having a second threshold voltage characteristic that is greater than the first threshold voltage characteristic, the second gate including a second material having a second-type work function that is opposite the first-type work function; and configuring the first device and the second device as a same channel type device.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 一种示例性方法包括提供基底; 在具有第一阈值电压特性的第一器件的衬底上形成第一栅极，所述第一栅极包括具有第一类型功函数的第一材料; 在所述衬底上形成具有大于所述第一阈值电压特性的第二阈值电压特性的第二器件的第二栅极，所述第二栅极包括具有与所述第一类型功函数相反的第二类型功函数的第二材料 ; 以及将所述第一设备和所述第二设备配置为相同的信道类型设备。

公开(公告)号：US20110195555A1

公开(公告)日：2011-08-11

申请号：US12702803

申请日：2010-02-09

Applicant: Chun Hsiung Tsai ,  Chien-Tai Chan ,  Mao-Rong Yeh ,  Da-Wen Lin

Inventor： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Mao-Rong Yeh ,  Da-Wen Lin

IPC: H01L21/336 ,  H01L21/265

CPC classification number: H01L29/66803 ,  H01L21/2236 ,  H01L21/2254 ,  H01L21/26526 ,  H01L21/26586

Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.

Abstract translation: 一种形成集成电路的方法包括提供半导体晶片，该半导体晶片包括在半导体晶片的表面上分配的半导体鳍; 在所述半导体鳍片的顶表面和侧壁上形成具有杂质的富掺杂层，其中所述杂质为n型或p型; 执行敲击植入以将杂质驱动到半导体鳍片中; 并除去富含掺杂剂的层。

公开(公告)号：US07986384B2

公开(公告)日：2011-07-26

申请号：US12357238

申请日：2009-01-21

Applicant: Chieh-Wen Lin ,  Kuan-Chih Chen ,  Kuo-Chao Chen

Inventor： Chieh-Wen Lin ,  Kuan-Chih Chen ,  Kuo-Chao Chen

IPC: G02F1/1333

CPC classification number: H01L29/78633 ,  G02F1/136209 ,  G02F2001/136231 ,  H01L27/124 ,  H01L27/1255

Abstract: A display panel is used with an image display system. The display panel includes a light-transmissive substrate, a gate insulating layer, a gate conductor, a first light-shielding structure, a channel layer and a second light-shielding structure. The gate insulating layer is formed over the light-transmissive substrate. The gate conductor and the first light-shielding structure are made of the same material, formed over the gate insulating layer, and electrically isolated from each other. The first light-shielding structure has a hollow portion. The channel layer and the second light-shielding structure made of the same material and formed over the light-transmissive substrate but under the gate insulating layer. The second light-shielding structure is disposed under the hollow portion of the first light-shielding structure.

Abstract translation: 显示面板与图像显示系统一起使用。 显示面板包括透光基板，栅极绝缘层，栅极导体，第一遮光结构，沟道层和第二遮光结构。 栅极绝缘层形成在透光基板上。 栅导体和第一遮光结构由形成在栅极绝缘层上并彼此电隔离的相同材料制成。 第一遮光结构具有中空部分。 沟道层和第二遮光结构由相同的材料制成并形成在透光基片上但栅极绝缘层下方。 第二遮光结构设置在第一遮光结构的中空部分的下方。

公开(公告)号：US07973284B2

公开(公告)日：2011-07-05

申请号：US12610362

申请日：2009-11-02

Applicant: Wen-Lin Chiang

Inventor： Wen-Lin Chiang

IPC: G02F1/01

CPC classification number: H04N1/482 ,  H01L31/02325

Abstract: An image sensing module includes a printed circuit board, an image sensor, and a color filter exchanging system. The image sensor positioned between the printed circuit board and the color filter exchanging system is assembled on the printed circuit board. The color filter exchanging system aligning with the image sensor fastens to the printed circuit board. The color filter exchanging system includes a stand, a driving module and a filter assembly. The stand fastening to the printed circuit board defines an opening revealing the image sensor. The driving module slides the filter assembly within the stand. The filter assembly includes a frame and a visible light bandpass filter and an infrared bandpass filter assembled to the frame. In different modes, the driving module drives the filter assembly so that the visible light bandpass filter or the infrared bandpass filter aligns with the image sensor by way of the opening.

Abstract translation: 图像感测模块包括印刷电路板，图像传感器和滤色器交换系统。 定位在印刷电路板和滤色片交换系统之间的图像传感器组装在印刷电路板上。 与图像传感器对准的滤色片更换系统固定在印刷电路板上。 滤色器交换系统包括支架，驱动模块和过滤器组件。 固定在印刷电路板上的支架限定了一个露出图像传感器的开口。 驱动模块将过滤器组件滑入支架内。 滤波器组件包括框架和可见光带通滤波器以及组装到框架上的红外带通滤波器。 在不同的模式下，驱动模块驱动过滤器组件，使得可见光带通滤镜或红外带通滤光片通过开口与图像传感器对准。

公开(公告)号：US20110142715A1

公开(公告)日：2011-06-16

申请号：US12653304

申请日：2009-12-11

Applicant: Wen Lin Lo ,  Xiao Ming Peng

Inventor： Wen Lin Lo ,  Xiao Ming Peng

IPC: C22C9/04

CPC classification number: C22C9/04

Abstract: The present invention provides an environmental friendly brass alloy, including 0.4 to 0.8 wt % of aluminum; 0.6 to 1.6 wt % of nickel; 0.8 to 2.0 wt % of tin; more than 95.6 wt % of copper and zinc; and less than 0.1 wt % of iron, lead, phosphorous and impurities, wherein the copper is present in an amount ranging from 60 to 68 wt %.

Abstract translation: 本发明提供一种环保型黄铜合金，其包含0.4〜0.8重量％的铝; 0.6〜1.6重量％的镍; 0.8〜2.0重量％的锡; 大于95.6重量％的铜和锌; 和小于0.1重量％的铁，铅，磷和杂质，其中铜以60至68重量％的量存在。