公开(公告)号：US07978548B2

公开(公告)日：2011-07-12

申请号：US12320625

申请日：2009-01-30

申请人： Yong-ho Cho

发明人： Yong-ho Cho

IPC分类号： G11C29/00

CPC分类号： G11C29/842 ,  G11C8/12

摘要： A block decoding circuit of a semiconductor memory device includes a plurality of block decoders, a plurality of repair address check circuits, a dummy repair address check circuit and a block selection signal generation circuit. The plurality of block decoders are configured to decode a received block selection address. The plurality of repair address check circuits are configured to generate second output signals based on whether a received block selection address and word line selection address are repair addresses. The dummy repair address check circuit is configured to generate a control signal in response to the block selection address and the word line selection address. The block selection signal generation circuit is configured to generate block selection signals based on the first output signals from the plurality of block decoders, the control signal from the dummy repair address circuit, and the second output signals from the repair address check circuits.

摘要翻译： 半导体存储器件的块解码电路包括多个块解码器，多个修复地址校验电路，虚拟修复地址校验电路和块选择信号生成电路。 多个块解码器被配置为对接收到的块选择地址进行解码。 多个修复地址检查电路被配置为基于接收的块选择地址和字线选择地址是修复地址来生成第二输出信号。 虚拟修复地址检查电路被配置为响应于块选择地址和字线选择地址而产生控制信号。 块选择信号生成电路被配置为基于来自多个块解码器的第一输出信号，来自虚拟修复地址电路的控制信号和来自修复地址检查电路的第二输出信号来生成块选择信号。

公开(公告)号：US20100194412A1

公开(公告)日：2010-08-05

申请号：US12700383

申请日：2010-02-04

申请人： Yong-ho Cho

发明人： Yong-ho Cho

IPC分类号： G01R27/08

CPC分类号： G11C5/147

摘要： A semiconductor device includes a comparator, an internal voltage generator, a control signal generator, and a selector. The comparator may compare a reference voltage to an internal voltage and output a comparison signal. The internal voltage generator may generate and output the internal voltage in response to the comparison signal. The control signal generator may generate a control signal. The selector may receive first and second target voltages, and select and output one of the first and second target voltages as the reference voltage in response to the control signal.

摘要翻译： 半导体器件包括比较器，内部电压发生器，控制信号发生器和选择器。 比较器可以将参考电压与内部电压进行比较，并输出比较信号。 内部电压发生器可以响应于比较信号而产生和输出内部电压。 控制信号发生器可以产生控制信号。 选择器可以接收第一和第二目标电压，并且响应于控制信号选择并输出第一和第二目标电压中的一个作为参考电压。

公开(公告)号：US07736188B2

公开(公告)日：2010-06-15

申请号：US11566498

申请日：2006-12-04

申请人： Seunghyun Bang ,  Jaesik Chung ,  Yong-ho Cho

发明人： Seunghyun Bang ,  Jaesik Chung ,  Yong-ho Cho

IPC分类号： H01R24/00

CPC分类号： H01M2/204 ,  H01M2/10 ,  H01M2/266 ,  H01M10/425

摘要： Disclosed herein are an electrode connector including a conductive wire and a plurality of plates mounted on the wire such that the plates can be electrically connected to electrodes of cells, wherein the plates are electrically connected to the wire in a structure in which the plates are coupled to the wire by clamping, and a surface (A) of each plate contacting the wire is plated with the same metal (a) as the wire while a surface (B) of each plate connected to the corresponding electrode of each cell is plated with the same metal (b) as the corresponding electrode of each cell, and a battery module constructed with the electrode connector.

摘要翻译： 本文公开了一种电极连接器，其包括导线和安装在线上的多个板，使得板可以电连接到电池的电极，其中板以与板耦合的结构电连接到导线 通过夹持而接合到线上，并且与导线接触的每个板的表面（A）镀有与线相同的金属（a），同时连接到每个电池的相应电极的每个板的表面（B）镀有 与每个电池的相应电极相同的金属（b）和由电极连接器构成的电池模块。

公开(公告)号：US07616037B2

公开(公告)日：2009-11-10

申请号：US12027716

申请日：2008-02-07

申请人： Yong-ho Cho

发明人： Yong-ho Cho

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2227

摘要： A method and apparatus for controlling a power-down mode of a delay locked loop (DLL), in which the apparatus includes a first switch unit, a DLL, and a second switch unit. The first switch unit transfers a first clock signal in response to a clock input enable signal. The DLL receives the first clock signal through the first switch unit to generate a second clock signal and is turned off by a power-down signal that is generated from the first clock signal latched by the first switch unit. The second switch unit transfers the second clock signal in response to a clock output enable signal. In a power-down mode, the clock input enable signal is deactivated in response to a clock enable signal and the clock output enable signal is deactivated after a predetermined number of clock cycles that are necessary for the latched first clock signal to be completely transferred through the delay cells of the DLL to an output terminal of the DLL. In a power-down exit mode, the power-down signal is deactivated in response to the clock enable signal and the clock input enable signal and the clock output enable signal are activated after a predetermined number of clock cycles that are necessary for the latched second clock signal to be completely transferred through the delay cells of the DLL to the output terminal of the DLL.

摘要翻译： 一种用于控制延迟锁定环（DLL）的掉电模式的方法和装置，其中该装置包括第一开关单元，DLL和第二开关单元。 第一开关单元响应于时钟输入使能信号传送第一时钟信号。 DLL通过第一开关单元接收第一时钟信号以产生第二时钟信号，并且由从第一开关单元锁存的第一时钟信号产生的掉电信号截止。 第二开关单元响应于时钟输出使能信号传送第二时钟信号。 在掉电模式下，时钟输入使能信号被响应于时钟使能信号被去激活，并且时钟输出使能信号在锁存的第一时钟信号必须被完全传送通过的预定数量的时钟周期之后被去激活 DLL的延迟单元到DLL的输出端。 在掉电退出模式中，响应于时钟使能信号，掉电信号被去激活，并且时钟输入使能信号和时钟输出使能信号在锁存的第二个所需的预定数量的时钟周期之后被激活 时钟信号通过DLL的延迟单元完全传输到DLL的输出端。

公开(公告)号：US20090175092A1

公开(公告)日：2009-07-09

申请号：US12275692

申请日：2008-11-21

申请人： Yong-ho Cho

发明人： Yong-ho Cho

IPC分类号： G11C8/18 ,  G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/222

摘要： A semiconductor memory device includes a command buffer that receives an external command and outputs a first command signal, a clock buffer that receives an external clock signal and outputs a first internal clock signal, a delay measurement and initialization unit that receives the first internal clock signal and a fourth internal clock signal and responsively outputs a second internal clock signal and a plurality of delayed signals corresponding to a delay time between when the external clock signal is input and data is output, a delay locked loop that receives the second internal clock signal and outputs a third internal clock signal and the fourth internal clock signal, a latency signal generation unit that delays the first command signal by a delay time between when the second internal clock signal is input to the delay locked loop and when the third internal clock signal is output from the delay locked loop, and then outputs the delayed first command signal as a latency signal, in response to the second and third internal clock signals and the delayed signals, and a data output buffer that outputs the data in response to the latency signal and the third internal clock signal.

摘要翻译： 半导体存储器件包括：命令缓冲器，其接收外部命令并输出第一命令信号，时钟缓冲器，其接收外部时钟信号并输出​​第一内部时钟信号;延迟测量和初始化单元，其接收第一内部时钟信号 和第四内部时钟信号，并且响应于输出对应于输入外部时钟信号和输出数据之间的延迟时间的第二内部时钟信号和多个延迟信号;接收第二内部时钟信号的延迟锁定环;以及 输出第三内部时钟信号和第四内部时钟信号;等待时间信号生成单元，用于在第二内部时钟信号输入到延迟锁定环之间的延迟时间和第三内部时钟信号为 从延迟锁定环输出，然后输出延迟的第一命令信号作为等待时间信号， 响应于第二和第三内部时钟信号和延迟信号，以及数据输出缓冲器，其响应于等待时间信号和第三内部时钟信号输出数据。