Reduced footprint pixel response correction systems and methods

    公开(公告)号:US10242649B2

    公开(公告)日:2019-03-26

    申请号:US15664940

    申请日:2017-07-31

    Applicant: Apple Inc.

    Abstract: Systems and methods for improving displayed image quality of an electronic display including a display pixel and a display driver are provided. A display pipeline receives input image data that indicates target luminance of the display pixel when displaying an image frame on the electronic display; determines a first bit group in pixel response corrected image data by mapping a first bit group in the input image data based at least in part on a first pixel response correction look-up-table; determines a second bit group in the pixel response corrected image data by mapping a second bit group in the input image data based at least in part on a second pixel response correction look-up-table; and outputs the pixel response corrected image data to the display driver to enable the display driver to facilitate displaying the image frame by writing the display pixel based on the pixel response corrected image data.

    DYNAMIC ALLOCATION OF DYNAMIC BINS FOR VARIABLE DYNAMIC RANGE IMAGE CONTENT

    公开(公告)号:US20240331119A1

    公开(公告)日:2024-10-03

    申请号:US18742998

    申请日:2024-06-13

    Applicant: Apple Inc.

    CPC classification number: G06T5/92 G06T5/40 G06T2207/20208

    Abstract: Methods and systems include determining an upper boundary of brightness values of high-dynamic range image content. Using the determined upper boundary, end points of bins of histogram values are determined. Using the determined end points of the bins of histogram values, luma values are allocated to the bins. The high-dynamic range image content is processed based at least in part on the allocations to the bins. Image data including the processed high-dynamic range image content is displayed via an electronic display.

    BACKLIGHT RECONSTRUCTION AND COMPENSATION
    45.
    发明公开

    公开(公告)号:US20240029687A1

    公开(公告)日:2024-01-25

    申请号:US18478588

    申请日:2023-09-29

    Applicant: Apple Inc.

    CPC classification number: G09G5/10 G09G3/2003 G09G2320/0233 G09G2310/0237

    Abstract: A processor or other circuitry may obtain emissive element strength information for an array of emissive elements of an electronic display. The processor or other circuitry may reconstruct backlight information at multiple locations within the electronic display. The processor or other circuitry also compensates display of image data based at least in part on the reconstructed backlight information.

    Efficient color mapping systems and methods

    公开(公告)号:US11361476B2

    公开(公告)日:2022-06-14

    申请号:US17020705

    申请日:2020-09-14

    Applicant: Apple Inc.

    Abstract: An electronic device may include a display panel with pixels that present an image based on image data and an application processor that generates the image data. The electronic device may include a display pipeline coupled to the electronic display and the application processor. The display pipeline may receive first image data from the application processor corresponding to a first color space used by the application processor. The display pipeline may apply a color mapping relationship to the first image data to generate second image data. The color mapping relationship may define a transform to apply to the first image data to generate the second image data corresponding to a second color space used by the electronic display. The display pipeline may transmit the second image data to a display driver that operates the electronic display to emit light according to the second image data.

    DYNAMIC ALLOCATION OF DYNAMIC BINS FOR VARIABLE DYNAMIC RANGE IMAGE CONTENT

    公开(公告)号:US20220067891A1

    公开(公告)日:2022-03-03

    申请号:US17362923

    申请日:2021-06-29

    Applicant: Apple Inc.

    Abstract: Methods and systems include determining an upper boundary of brightness values of high-dynamic range image content. Using the determined upper boundary, end points of bins of histogram values are determined. Using the determined end points of the bins of histogram values, luma values are allocated to the bins. The high-dynamic range image content is processed based at least in part on the allocations to the bins. Image data including the processed high-dynamic range image content is displayed via an electronic display.

    HARDWARE ACCELERATORS USING SHARED INTERFACE REGISTERS

    公开(公告)号:US20220066828A1

    公开(公告)日:2022-03-03

    申请号:US17149422

    申请日:2021-01-14

    Applicant: Apple Inc.

    Abstract: Methods and systems include processors and hardware accelerators. The processor initiates a first process in a first hardware accelerator configured to aid the processor in performing the first process. The processor initiates the first process using one or more interface registers. The processor performs additional processing while the first hardware accelerator performs the first process after initiation of the first process. The processor also initiates a second process in a second hardware accelerator configured to aid the processor in performing a second process. Moreover, the processor initiates the second process using the one or more interface registers.

    Electronic display partial image frame update systems and methods

    公开(公告)号:US10978027B2

    公开(公告)日:2021-04-13

    申请号:US16828824

    申请日:2020-03-24

    Applicant: Apple Inc.

    Abstract: An electronic device may include a display panel and an image data source designed to determine a differing region in the image frame by comparing source image data and image data corresponding with a previous image frame. The electronic device may also include a display pipeline between the image data source and the display panel. The display pipeline may include image processing circuitry to convert image data from a source space to a display space and image processing circuitry to spatially process the image data. The display pipeline may determine a crop region by converting the differing region to the display space and determine a partial frame region, based on the image data to be spatially processed, by the image processing circuitry. The display pipeline may also determine and retrieve a fetch region smaller than the image frame by converting the partial frame region to the source space.

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