公开(公告)号：US20240215344A1

公开(公告)日：2024-06-27

申请号：US17788605

申请日：2021-08-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yu Feng ,  Libin Liu ,  Jiangnan Lu

IPC: H10K59/131 ,  G09G3/32

CPC classification number: H10K59/131 ,  G09G3/32 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/0247

Abstract: An array substrate is provided. A respective pixel driving circuit of the array substrate includes a driving transistor, a storage capacitor, and a transistor having a gate electrode connected to a respective second gate line of a plurality of second gate lines, a first electrode connected to a first capacitor electrode of the storage capacitor, and a second electrode connected to a second electrode of a first reset transistor, the transistor being configured to receive a reset signal through the first reset transistor. An active layer of the driving transistor and an active layer of the transistor are spaced apart from each other by at least an insulating layer. The active layer of the driving transistor comprises a first semiconductor material. The active layer of the transistor comprises a second semiconductor material different from the first semiconductor material.

公开(公告)号：US12002425B2

公开(公告)日：2024-06-04

申请号：US18038690

申请日：2020-11-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lujiang Huangfu ,  Li Wang ,  Jianchao Zhu ,  Libin Liu

IPC: G09G3/3233 ,  G09G3/3291

CPC classification number: G09G3/3233 ,  G09G3/3291 ,  G09G2300/0852 ,  G09G2310/061 ,  G09G2320/0247 ,  G09G2330/021

Abstract: Provided are a pixel circuit and a driving method therefor, and a display apparatus. The pixel circuit includes a drive transistor, a reset circuit, a data writing circuit, a storage capacitor circuit, a threshold value compensation circuit, a conduction control circuit, a light-emitting control circuit, and a light-emitting device; the conduction control circuit is configured to: conduct the threshold value compensation circuit with the gate of the drive transistor, and conduct the reset circuit with the gate of the drive transistor at the reset stage, the threshold value detecting stage and the data writing stage; and cut off a conducting state of the threshold value compensation circuit with the gate of the drive transistor, and cut off a conducting state of the reset circuit with the gate of the drive transistor at the driving stage; where the conduction control circuit includes an oxide semiconductor thin film transistor.

公开(公告)号：US20240177660A1

公开(公告)日：2024-05-30

申请号：US17789174

申请日：2021-09-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lujiang Huangfu ,  Li Wang ,  Jianchao Zhu ,  Libin Liu ,  Yu Feng

IPC: G09G3/3233

CPC classification number: G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/08 ,  G09G2320/0247

Abstract: A pixel driving circuit is provided. The pixel driving circuit includes a storage capacitor (Cst) having a first capacitor electrode (Ce1) and a second capacitor electrode (Ce2); a driving transistor (Td) configured to generate a driving current; and a switch (SW) configured to control connection or disconnection between a gate electrode of the driving transistor (Td) and the first capacitor electrode (Ce1).

公开(公告)号：US11963407B2

公开(公告)日：2024-04-16

申请号：US17427076

申请日：2020-11-13

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan Lu ,  Guangliang Shang ,  Can Zheng ,  Yu Feng ,  Libin Liu ,  Jie Zhang ,  Mei Li

IPC: H10K59/131 ,  G09G3/3208 ,  H10K59/121

CPC classification number: H10K59/131 ,  H10K59/121 ,  G09G3/3208 ,  G09G2320/0209 ,  G09G2320/0233

Abstract: Provided is an organic light-emitting diode display substrate, including: a source/drain layer, a planarization layer and an anode layer which are laminated in sequence, wherein the source/drain layer includes at least one pair of first signal lines; the anode layer includes a common power line, wherein the common power line is provided with vent holes; overlapping areas between two first signal lines in each pair of the first signal lines and a projection pattern of the vent hole are equal, the overlapping area being greater than 0, wherein the projection pattern of the vent hole is a pattern of an orthographic projection of the vent hole in the common power line on the source/drain layer. A display panel and a display device are also provided.

公开(公告)号：US11915655B2

公开(公告)日：2024-02-27

申请号：US17631780

申请日：2021-03-05

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan Lu ,  Guangliang Shang ,  Xinshe Yin ,  Libin Liu ,  Ke Feng

IPC: G09G3/3266 ,  G11C19/28

CPC classification number: G09G3/3266 ,  G11C19/28 ,  G09G2300/0408 ,  G09G2310/0286

Abstract: A shift register unit, a method for driving a shift register unit, a gate driving circuit, and a display device are provided. The shift register unit includes: an input control circuit, configured to control a level of the first node; a first control circuit, configured to control a level of the second node; a second control circuit, configured to control the level of the second node under control of a fourth clock signal and an output signal; an output circuit, configured to control a level of the output terminal under control of the level of the first node and the level of the second node; and a first reset circuit, configured to control the level of the output terminal under control of the first enable signal, so as to allow the output terminal to stably output a non-operating level during a detection phase.

公开(公告)号：US11869424B2

公开(公告)日：2024-01-09

申请号：US17415758

申请日：2020-12-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Libin Liu ,  Yu Feng ,  Shiming Shi

IPC: G09G3/3233

CPC classification number: G09G3/3233 ,  G09G2300/0439 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2320/0233

Abstract: The present disclosure relates to the field of display technology, and proposes a pixel driving circuit, a pixel structure, and a display panel. The pixel driving circuit includes a plurality of driving transistors. For each driving transistor the first terminal is connected to a first power terminal, the second terminal is connected to a first node, and the control terminal is connected to a second node, so as to input current to the first node under the effect of the voltage at the second node. The low pixel density area of the display panel can be provided with the above-mentioned pixel driving circuit, so that the brightness difference between the low pixel density area and the high pixel density area can be avoided.

公开(公告)号：US11837169B2

公开(公告)日：2023-12-05

申请号：US17744709

申请日：2022-05-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yipeng Chen ,  Libin Liu ,  Lujiang Huangfu

IPC: G09G3/3258 ,  G09G3/20 ,  G09G3/3291 ,  G09G3/3233

CPC classification number: G09G3/3258 ,  G09G3/2092 ,  G09G3/3291 ,  G09G3/3233 ,  G09G2300/0819 ,  G09G2320/045

Abstract: The present disclosure provides a pixel circuit including: a driving transistor and a voltage control circuit; wherein in the voltage control circuit, at least one transistor directly coupled to a gate of the driving transistor is an oxide thin film transistor. The disclosure also provides a display substrate and a display apparatus.

公开(公告)号：US20230371319A1

公开(公告)日：2023-11-16

申请号：US18223660

申请日：2023-07-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Libin Liu ,  Qian Yang

IPC: H10K59/126 ,  H10K59/131 ,  H10K59/121

CPC classification number: H10K59/126 ,  H10K59/1213 ,  H10K59/131 ,  H01L27/124

Abstract: The present disclosure provides a display substrate, a display panel including the display substrate, and an electronic device. The display substrate includes: a base substrate; a transistor on the base substrate, wherein the transistor includes a first gate layer; a signal line located on the base substrate and configured to transmit an electrical signal; and a conductive isolation portion located between the transistor and the signal line adjacent to the transistor in a direction parallel to the base substrate, wherein the conductive isolation portion is electrically connected with a DC source signal on the display substrate.

公开(公告)号：US11763740B2

公开(公告)日：2023-09-19

申请号：US17762330

申请日：2021-04-15

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Libin Liu ,  Tian Dong ,  Jiangnan Lu ,  Shiming Shi

IPC: G09G3/20 ,  G09G3/3208 ,  G11C19/28 ,  G09G3/3225

CPC classification number: G09G3/3225 ,  G11C19/28 ,  G09G2300/0426 ,  G09G2300/0852 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2320/0247

Abstract: The present disclosure provides a signal generation circuit, a signal generation method, a signal generation module and a display device. The signal generating circuit includes an input terminal, a signal output terminal, a transmission control circuit, a first output circuit, and an output control circuit; the output control circuit is electrically connected to a first output control terminal, a second output control terminal, a second voltage terminal, the signal writing-in terminal, the signal output terminal and the first voltage terminal, configured to control to connect the signal writing-in terminal and the second voltage terminal under the control of a second output control signal provided by the second output control terminal, and control to connect the signal output terminal and the first voltage terminal under the control of a first output control signal provided by the first output control terminal. The present disclosure expands an adjustment range of frequency of a PWM signal.

公开(公告)号：US11751460B2

公开(公告)日：2023-09-05

申请号：US17762962

申请日：2021-04-15

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yipeng Chen ,  Lujiang Huangfu ,  Libin Liu

IPC: H10K59/131 ,  H10K59/35 ,  G09G3/3233 ,  H10K59/126 ,  H10K59/12

CPC classification number: H10K59/353 ,  G09G3/3233 ,  H10K59/126 ,  H10K59/131 ,  H10K59/352 ,  G09G2300/0452 ,  G09G2300/0842 ,  H10K59/1201

Abstract: A display panel, a method of manufacturing the same, and a display device are provided. In the display panel, sub-pixel areas in a same row along a first direction are divided into a plurality of sub-pixel area groups independent from each other, and each sub-pixel area group includes at least two adjacent sub-pixel areas, a connection layer includes a connection pattern arranged in each sub-pixel area, and the connection pattern is coupled to the initialization signal line pattern in the sub-pixel area wherein the connection pattern is located, connection patterns located in a same sub-pixel area group are sequentially coupled along the first direction to form the connection portion; at least part of a first auxiliary signal line layer is located in an anode spacing area, and is insulated from an anode pattern, the connection pattern in each sub-pixel area group is coupled to the first auxiliary signal line layer.