公开(公告)号：US20130087859A1

公开(公告)日：2013-04-11

申请号：US13253268

申请日：2011-10-05

申请人： Yue Liang ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yanfeng Wang

发明人： Yue Liang ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yanfeng Wang

IPC分类号： H01L21/266 ,  H01L27/092

CPC分类号： H01L27/092 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/517

摘要： A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.

摘要翻译： 一种在半导体衬底上包括p型半导体器件和n型半导体器件的器件。 n型半导体器件包括具有高k栅极电介质的栅极结构。 在n型半导体器件的栅极结构的高k栅极电介质和半导体衬底之间的界面处存在浓度范围为1×1016原子/ cm3至1×1021原子/ cm3的碳掺杂剂。 还公开了形成上述装置的方法。

公开(公告)号：US20110272779A1

公开(公告)日：2011-11-10

申请号：US13189016

申请日：2011-07-22

申请人： Deok-Kee Kim ,  Dureseti Chidambarrao ,  William K. Henson ,  Chandrasekharan Kothandaraman

发明人： Deok-Kee Kim ,  Dureseti Chidambarrao ,  William K. Henson ,  Chandrasekharan Kothandaraman

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.

摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

公开(公告)号：US07943493B2

公开(公告)日：2011-05-17

申请号：US12873882

申请日：2010-09-01

申请人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman

发明人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman

IPC分类号： H01L21/20

CPC分类号： H01L23/5256 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.

摘要翻译： 在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。 连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。 蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。 去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。 形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。 在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。

公开(公告)号：US20100330783A1

公开(公告)日：2010-12-30

申请号：US12873882

申请日：2010-09-01

申请人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman

发明人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman

IPC分类号： H01L21/20

CPC分类号： H01L23/5256 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.

摘要翻译： 在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。 连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。 蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。 去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。 形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。 在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。

公开(公告)号：US20100258875A1

公开(公告)日：2010-10-14

申请号：US12823225

申请日：2010-06-25

申请人： Bruce Bennett Doris ,  William K. Henson ,  Richard Stephen Wise ,  Hongwen Yan

发明人： Bruce Bennett Doris ,  William K. Henson ,  Richard Stephen Wise ,  Hongwen Yan

IPC分类号： H01L27/088

CPC分类号： H01L21/823842

摘要： A semiconductor structure. The semiconductor structure includes: a first semiconductor region and a second semiconductor region; a first gate dielectric region on the first semiconductor region; a second gate dielectric region on the second semiconductor region, wherein the second semiconductor region includes a first top surface shared by the second semiconductor region and the second gate dielectric region, and wherein the first top surface defines a reference direction perpendicular to the first top surface and pointing from inside to outside of the second semiconductor region; an electrically conductive layer on the first gate dielectric region; a first poly-silicon region on the electrically conductive layer; a second poly-silicon region on the second gate dielectric region; a first hard mask region on the first poly-silicon region; and a second hard mask region on the second poly-silicon region.

摘要翻译： 半导体结构。 半导体结构包括：第一半导体区域和第二半导体区域; 在所述第一半导体区域上的第一栅极电介质区域; 在所述第二半导体区域上的第二栅极电介质区域，其中所述第二半导体区域包括由所述第二半导体区域和所述第二栅极电介质区域共享的第一顶表面，并且其中所述第一顶表面限定垂直于所述第一顶表面的参考方向 并从第二半导体区域的内部指向外部; 在所述第一栅极电介质区域上的导电层; 导电层上的第一多晶硅区; 在所述第二栅极电介质区域上的第二多晶硅区域; 第一多晶硅区域上的第一硬掩模区域; 以及第二多晶硅区域上的第二硬掩模区域。

公开(公告)号：US07632724B2

公开(公告)日：2009-12-15

申请号：US11673716

申请日：2007-02-12

申请人： Dureseti Chidambarrao ,  William K. Henson ,  Yaocheng Liu

发明人： Dureseti Chidambarrao ,  William K. Henson ,  Yaocheng Liu

IPC分类号： H01L21/00

CPC分类号： H01L29/78603 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7843

摘要： A method is provided for fabricating a field effect transistor (“FET”) having a channel region in a semiconductor-on-insulator (“SOI”) layer of an SOI substrate. Desirably, in such method, a sacrificial stressed layer is formed to overlie a first portion of an active semiconductor region but not overlie second portion of the active semiconductor region which shares a common boundary with the first portion. After forming trenches in the SOI layer, the SOI substrate is heated with the stressed layer thereon sufficiently to cause the stressed layer to relax, thereby causing the stressed layer to apply a first stress to the first portion and to apply a second stress to the second portion. For example, when the first stress is tensile, the second stress is compressive, or the first stress can be compressive when the second stress is tensile. Desirably, the stressed layer is then removed to expose the first and second portions of the active semiconductor region. Desirably, the field effect transistor (“FET”) is formed to include (i) a source region in the first portion, (ii) a drain region in the first portion, and (iii) a channel region in the second portion.

摘要翻译： 提供一种用于制造在SOI衬底的绝缘体上半导体（“SOI”）层中具有沟道区的场效应晶体管（“FET”）的方法。 理想地，在这种方法中，牺牲应力层形成为覆盖有源半导体区域的第一部分，但不覆盖与第一部分共用共同边界的有源半导体区域的第二部分。 在SOI层中形成沟槽之后，将SOI衬底上的应力层充分加热，使得应力层松弛，从而使应力层对第一部分施加第一应力并向第二部分施加第二应力 一部分。 例如，当第一应力是拉伸时，第二应力是压缩的，或者当第二应力是拉伸时，第一应力可以是压缩的。 理想地，应力层被去除以暴露有源半导体区域的第一和第二部分。 期望地，场效应晶体管（“FET”）形成为包括（i）第一部分中的源极区域，（ii）第一部分中的漏极区域，以及（iii）第二部分中的沟道区域。

公开(公告)号：US07605077B2

公开(公告)日：2009-10-20

申请号：US11308486

申请日：2006-03-29

申请人： William K. Henson ,  Kern Rim ,  Jack A. Mandelman

发明人： William K. Henson ,  Kern Rim ,  Jack A. Mandelman

IPC分类号： H01L21/40 ,  H01L29/45

CPC分类号： H01L21/823443 ,  H01L21/82345 ,  H01L21/823835 ,  H01L21/823842

摘要： An integration scheme that enables full silicidation (FUSI) of the nFET and pFET gate electrodes at the same time as that of the source/drain regions is provided. The FUSI of the gate electrodes eliminates the gate depletion problem that is observed with polysilicon gate electrodes. In addition, the inventive integration scheme creates different silicon thicknesses of the gate electrode just prior to silicidation. This feature of the present invention allows for fabricating nFETs and pFETs that have a band edge workfunction that is tailored for the specific device region.

摘要翻译： 提供了与源极/漏极区域同时实现nFET和pFET栅电极的全硅化（FUSI）的集成方案。 栅电极的FUSI消除了多晶硅栅电极观察到的栅耗尽问题。 此外，本发明的集成方案刚好在硅化之前产生栅电极的不同硅厚度。 本发明的该特征允许制造具有针对特定器件区域定制的带边缘功能函数的nFET和pFET。

公开(公告)号：US20090179283A1

公开(公告)日：2009-07-16

申请号：US11954918

申请日：2007-12-12

申请人： Charlotte D. Adams ,  Bruce B. Doris ,  Philip Fisher ,  William K. Henson ,  Jeffrey W. Sleight

发明人： Charlotte D. Adams ,  Bruce B. Doris ,  Philip Fisher ,  William K. Henson ,  Jeffrey W. Sleight

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/78

摘要： A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed on the semiconductor substrate. Oxygen-impermeable dielectric spacers are formed on the sidewalls of the semiconductor gate stack and the high-k material metal gate stack. The oxygen-impermeable dielectric spacer on the semiconductor gate stack is removed, while the oxygen impermeable dielectric spacer on the high-k material metal gate electrode is preserved. A low-k dielectric spacer is formed on the semiconductor gate stack, which provides a low parasitic capacitance for the device employing the semiconductor gate stack.

摘要翻译： 包括基于氧化硅的栅极电介质和掺杂的半导体材料的半导体栅极堆叠形成在半导体衬底上。 还在半导体衬底上形成包括高k栅极电介质和金属栅极部分的高k材料金属栅电极。 在半导体栅极堆叠和高k材料金属栅极堆叠的侧壁上形成氧气不可渗透的电介质间隔物。 除去半导体栅极堆叠上的不透氧电介质间隔物，同时保留高k材料金属栅电极上的不透氧电介质间隔物。 在半导体栅极叠层上形成一个低k电介质隔离层，为采用半导体栅极堆叠的器件提供了低寄生电容。

公开(公告)号：US20090090993A1

公开(公告)日：2009-04-09

申请号：US11867268

申请日：2007-10-04

申请人： William K. Henson ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman ,  Byeongju Park

发明人： William K. Henson ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman ,  Byeongju Park

IPC分类号： H01L29/00 ,  H01L21/02

CPC分类号： H01L23/5256 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated eFUSE device is formed by forming a silicon “floating beam” on air, whereupon the fusible portion of the eFUSE device resides. This beam extends between two larger, supporting terminal structures. “Undercutting” techniques are employed whereby a structure is formed atop a buried layer, and that buried layer is removed by selective etching. Whereby a “floating” silicide eFUSE conductor is formed on a silicon beam structure. In its initial state, the eFUSE silicide is highly conductive, exhibiting low electrical resistance (the “unblown state of the eFUSE). When a sufficiently large current is passed through the eFUSE conductor, localized heating occurs. This heating causes electromigration of the silicide into the silicon beam (and into surrounding silicon, thereby diffusing the silicide and greatly increasing its electrical resistance. When the current source is removed, the silicide remains permanently in this diffused state, the “blown” state of the eFUSE.

摘要翻译： 通过在空气中形成硅“浮动光束”形成集成eFUSE装置，于是eFUSE装置的可熔部分驻留。 该梁在两个更大的支撑端子结构之间延伸。 采用“底切”技术，由此在掩埋层顶部形成结构，并且通过选择性蚀刻去除掩埋层。 由此在硅梁结构上形成“浮动”硅化物eFUSE导体。 在初始状态下，eFUSE硅化物具有高导电性，表现出较低的电阻（eFUSE的未吹出状态），当足够大的电流通过eFUSE导体时，发生局部加热，该加热导致硅化物的电迁移 （并且进入周围的硅，从而扩散硅化物并大大增加其电阻。当电流源被去除时，硅化物永久地保持在这种扩散状态，eFUSE的“吹”状态。

公开(公告)号：US07202513B1

公开(公告)日：2007-04-10

申请号：US11162953

申请日：2005-09-29

申请人： Dureseti Chidambarrao ,  William K. Henson ,  Kern Rim ,  William C. Wille

发明人： Dureseti Chidambarrao ,  William K. Henson ,  Kern Rim ,  William C. Wille

IPC分类号： H01L31/00

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/0653 ,  H01L29/7842

摘要： A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of stress are achieved when the method is applied to a selective SOI architecture.

摘要翻译： 描述了一种使用高应力氮化物膜与选择性绝缘体上半导体（SOI）器件结构结合的在不同导电性的MOS晶体管的沟道中应力的方法。 描述了在浅沟槽隔离（STI）工艺中使用压缩和拉伸氮化物膜的方法。 当将该方法应用于选择性SOI结构时，实现高应力值。