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41.发明授权Lateral P-I-N photodiode element with high quantum efficiency for a CMOS image sensor 有权用于CMOS图像传感器的具有高量子效率的横向P-I-N光电二极管元件公开(公告)号：US06323054B1
公开(公告)日：2001-11-27
申请号：US09583398
申请日：2000-05-31
IPC分类号： H01L2100
CPC分类号： H01L27/14609
摘要： A process for fabricating a lateral photodiode element, for an image sensor cell, with an increased depletion region, has been developed. The process features protecting a portion of the semiconductor substrate from ion implantation procedures used to create the P well, and the N well components of the lateral photodiode element. The protected region, or the space between the P well and N well regions, allows a larger depletion region to be realized, when compared to lateral photodiode elements in which the N well and P well regions butt. The space between the P well and N well regions, between about 0.2 to 0.4 um, result in the desired P well—intrinsic or P type semiconductor substrate—N well, (P-I-N), lateral photodiode element.
摘要翻译： 已经开发了用于图像传感器单元的具有增加的耗尽区域的横向光电二极管元件的制造方法。 该工艺特征是保护半导体衬底的一部分免受用于产生P阱的离子注入工艺和横向光电二极管元件的N阱部件。 与N阱和P阱区对接的横向光电二极管元件相比，受保护区域或P阱和N阱区域之间的空间允许实现更大的耗尽区域。 在P阱和N阱区之间的间隔在约0.2至0.4μm之间，导致所需的P本征或P型半导体衬底N阱（P-I-N），横向光电二极管元件。
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公开(公告)号：US20140061842A1
公开(公告)日：2014-03-06
申请号：US13604380
申请日：2012-09-05
申请人： Shyh-Fann Ting , Jiech-Fun Lu , Ming-I Wang , Yeur-Luen Tu , Ching-Chun Wang
发明人： Shyh-Fann Ting , Jiech-Fun Lu , Ming-I Wang , Yeur-Luen Tu , Ching-Chun Wang
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/1464 , H01L21/76838 , H01L27/14623 , H01L27/14687
摘要： A method includes forming an opening extending from a back surface of a semiconductor substrate to a metal pad on a front side of the semiconductor substrate, and forming a first conductive layer including a first portion overlapping active image sensors in the semiconductor substrate, a second portion overlapping black reference image sensors in the semiconductor substrate, and a third portion in the opening to contact the metal pad. A second conductive layer is formed over and contacting the first conductive layer. A first patterning step is performed to remove the first and the second portions of the second conductive layer, wherein the first conductive layer is used as an etch stop layer. A second patterning step is performed to remove a portion of the first portion of the first conductive layer. The second and the third portions of the first conductive layer remain after the second patterning step.
摘要翻译： 一种方法包括形成从半导体衬底的背表面延伸到半导体衬底的前侧上的金属焊盘的开口，以及在半导体衬底中形成包括与有源图像传感器重叠的第一部分的第一导电层，第二部分 半导体衬底中重叠的黑色参考图像传感器，以及开口中的与金属垫接触的第三部分。 在第一导电层上形成第二导电层并与第一导电层接触。 执行第一图案化步骤以去除第二导电层的第一和第二部分，其中第一导电层用作蚀刻停止层。 执行第二图案化步骤以去除第一导电层的第一部分的一部分。 在第二图案化步骤之后，第一导电层的第二和第三部分保留。
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公开(公告)号：US20080198454A1
公开(公告)日：2008-08-21
申请号：US11676388
申请日：2007-02-19
IPC分类号： G02B5/30
摘要： An image sensor device includes a semiconductor substrate having a front surface and a back surface, pixels formed on the front surface of the semiconductor substrate, and grid arrays aligned with one of the pixels. One of the grid arrays is configured to allow a wavelength of light to pass through to the corresponding one of the pixels. The grid arrays are disposed overlying the front or back surface of the semiconductor substrate.
摘要翻译： 图像传感器装置包括具有前表面和后表面的半导体衬底，形成在半导体衬底的前表面上的像素和与像素之一对准的栅格阵列。 网格阵列中的一个被配置为允许光的波长通过到相应的一个像素。 栅格阵列设置在半导体衬底的前表面或后表面上。
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公开(公告)号：US07368770B1
公开(公告)日：2008-05-06
申请号：US11349786
申请日：2006-02-07
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H01L27/14603
摘要： A semiconductor imager structure having a well region formed in a substrate layer. The well region being of a predetermined shape having a plurality of corners being non-right angles.
摘要翻译： 一种在衬底层中形成有阱区的半导体成像器结构。 井区具有预定形状，其中多个角是非直角。
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公开(公告)号：US07312484B1
公开(公告)日：2007-12-25
申请号：US11350298
申请日：2006-02-07
IPC分类号： H01L31/0328
CPC分类号： H01L27/14603
摘要： A semiconductor structure, having a doped well region being formed in a substrate layer and a transistor having a terminal provided within said doped well region. The semiconductor structure also includes an oxide layer formed over the substrate layer, the doped well region, a poly silicon region, and the terminal of the transistor. The oxide layer including a step region being located where a height of the oxide layer transitions from a height associated with the doped well region to a height associated with the terminal of the transistor.
摘要翻译： 一种半导体结构，其具有在衬底层中形成的掺杂阱区和在所述掺杂阱区内具有端子的晶体管。 半导体结构还包括在衬底层上形成的氧化物层，掺杂阱区，多晶硅区和晶体管的端子。 氧化物层包括步骤区域，其中氧化物层的高度从与掺杂阱区域相关联的高度转变到与晶体管的端子相关联的高度。
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公开(公告)号：US07180111B1
公开(公告)日：2007-02-20
申请号：US10752845
申请日：2004-01-07
IPC分类号： H01L31/113
CPC分类号： H01L27/14603
摘要： A photodiode sensor structure includes a first dopant type substrate with a first surface and a second dopant type well region with a second surface. The second dopant type well region is formed in the first dopant type substrate such that the first surface and the second surface are substantially co-planar to form a diode surface. An interface between the second dopant type well region and the first dopant type substrate at the diode surface forms a diode junction. A poly silicon region is formed along the periphery of the entire diode junction. The poly silicon region provides the p-n junction of the photodiode with a physical shield to prevent any process damage from being introduced after the poly silicon processing (including damages from processes such as dielectric deposition/pattern, metal deposition/pattern, and/or via/contact hole etching), thereby reducing leakage current. The poly silicon region can also provide the p-n junction of the photodiode with an electrical shield to prevent any possible trapped charges at higher levels of dielectric above the junctions to affect the surface potential and/or prevent the formation of conducting channels between the p-n regions, thereby reducing leakage current.
摘要翻译： 光电二极管传感器结构包括具有第一表面的第一掺杂剂型衬底和具有第二表面的第二掺杂剂型阱区。 第二掺杂剂型阱区形成在第一掺杂剂型衬底中，使得第一表面和第二表面基本上共面以形成二极管表面。 在二极管表面处的第二掺杂剂型阱区和第一掺杂剂型衬底之间的界面形成二极管结。 沿着整个二极管结的周边形成多晶硅区域。 多晶硅区域提供光电二极管的pn结与物理屏蔽，以防止在多晶硅处理之后引入任何工艺损坏（包括诸如介电沉积/图案，金属沉积/图案和/或通孔/ 接触孔蚀刻），从而减少漏电流。 多晶硅区域还可以提供光电二极管的pn结与电屏蔽，以防止在结点之上的较高电介质层处的任何可能的俘获电荷影响表面电势和/或防止在pn区域之间形成导电通道， 从而减少漏电流。
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公开(公告)号：US07173299B1
公开(公告)日：2007-02-06
申请号：US11350296
申请日：2006-02-07
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H01L27/14643 , H01L27/14603
摘要： A semiconductor imager structure having a photodiode being provided as a well region formed within a substrate layer and a transistor electrically connected to the photodiode and having a terminal that has a same electrical potential as the photodiode. The well region of the photodiode having an extended portion so that at least a portion of the terminal of the transistor has the same electrical potential as the photodiode is formed within the extended portion of the well region of the photodiode.
摘要翻译： 提供具有光电二极管作为形成在衬底层内的阱区的半导体成像器结构和与该光电二极管电连接且具有与该光电二极管具有相同电位的端子的晶体管。 光电二极管的阱区具有延伸部分，使得晶体管的端子的至少一部分具有与光电二极管的阱区域的延伸部分内的光电二极管相同的电位。
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48.发明授权Method for making spectrally efficient photodiode structures for CMOS color imagers 有权CMOS彩色成像器制作光谱效率高的光电二极管结构的方法公开(公告)号：US06707080B2
公开(公告)日：2004-03-16
申请号：US10320296
申请日：2002-12-16
IPC分类号： H01L31062
CPC分类号： H01L27/14645
摘要： A method for making an array of photodiodes with more uniform optical spectral response for the red, green, and blue pixel cells on a CMOS color imager is achieved. After forming a field oxide on a substrate to electrically isolate device areas for CMOS circuits, an array of deep N doped wells is formed for photodiodes for the long wavelength red pixel cells. An array of P doped well regions is formed adjacent to and interlaced with the N doped wells. Shallow diffused N+ regions are formed within the P doped wells for the shorter wavelength green and blue color pixels cells. The shallow diffused photodiodes improve the quantum efficiency (QE), and provide a color imager with improved color fidelity. An insulating layer and appropriate dye materials are deposited and patterned over the photodiodes to provide the array of color pixel cells. The N and P doped wells are also used for the supporting FET CMOS circuits to provide a cost-effective manufacturing process.
摘要翻译： 实现了对CMOS彩色成像器上的红色，绿色和蓝色像素单元制造具有更均匀的光谱响应的光电二极管阵列的方法。 在衬底上形成场氧化物以电隔离CMOS电路的器件区域后，形成用于长波长红色像素单元的光电二极管的深N掺杂阱的阵列。 与N个掺杂的阱相邻并且与其交错形成P掺杂阱区的阵列。 在较短波长的绿色和蓝色像素单元的P掺杂阱内形成浅扩散的N +区。 浅扩散光电二极管提高了量子效率（QE），并提供了具有改进的色彩保真度的彩色成像仪。 在光电二极管上沉积并图案化绝缘层和适当的染料材料以提供彩色像素单元阵列。 N和P掺杂阱也用于支持FET CMOS电路以提供成本有效的制造工艺。
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49.发明授权Method for making spectrally efficient photodiode structures for CMOS color imagers 有权CMOS彩色成像器制作光谱效率高的光电二极管结构的方法公开(公告)号：US06518085B1
公开(公告)日：2003-02-11
申请号：US09635584
申请日：2000-08-09
IPC分类号： H01L2100
CPC分类号： H01L27/14645
摘要： A method for making an array of photodiodes with more uniform optical spectral response for the red, green, and blue pixel cells on a CMOS color imager is achieved. After forming a field oxide on a substrate to electrically isolate device areas for CMOS circuits, an array of deep N doped wells is formed for photodiodes for the long wavelength red pixel cells. An array of P doped well regions is formed adjacent to and interlaced with the N doped wells. Shallow diffused N+ regions are formed within the P doped wells for the shorter wavelength green and blue color pixels cells. The shallow diffused photodiodes improve the quantum efficiency (QE), and provide a color imager with improved color fidelity. An insulating layer and appropriate dye materials are deposited and patterned over the photodiodes to provide the array of color pixel cells. The N and P doped wells are also used for the supporting FET CMOS circuits to provide a cost-effective manufacturing process.
摘要翻译： 实现了对CMOS彩色成像器上的红色，绿色和蓝色像素单元制造具有更均匀的光谱响应的光电二极管阵列的方法。 在衬底上形成场氧化物以电隔离CMOS电路的器件区域后，形成用于长波长红色像素单元的光电二极管的深N掺杂阱的阵列。 与N个掺杂的阱相邻并且与其交错形成P掺杂阱区的阵列。 在较短波长的绿色和蓝色像素单元的P掺杂阱内形成浅扩散的N +区。 浅扩散光电二极管提高了量子效率（QE），并提供了具有改进的色彩保真度的彩色成像仪。 在光电二极管上沉积并图案化绝缘层和适当的染料材料以提供彩色像素单元阵列。 N和P掺杂阱也用于支持FET CMOS电路以提供成本有效的制造工艺。
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