NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF
    41.
    发明申请
    NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF 审中-公开
    非易失性存储器及其制造方法

    公开(公告)号:US20090065846A1

    公开(公告)日:2009-03-12

    申请号:US11955396

    申请日:2007-12-13

    IPC分类号: H01L29/78 H01L21/336

    摘要: A manufacturing method of a non-volatile memory includes forming a first dielectric layer, a first conductive layer, and a first cap layer sequentially on a substrate to form first gate structures; conformally forming a second dielectric layer on the substrate; forming a first spacer having a larger wet etching rate than the second dielectric layer on each sidewall of each first gate structure; partially removing the first and second dielectric layers to expose the substrate. A third dielectric layer is formed on the substrate between the first gate structures; removing the first spacer; forming a second conductive layer on the third dielectric layer; removing the first cap layer and a portion of the first conductive layer to form second gate structures; and forming doped regions in the substrate at two sides of each second gate structure.

    摘要翻译: 非易失性存储器的制造方法包括在衬底上依次形成第一电介质层,第一导电层和第一覆盖层,以形成第一栅极结构; 在基底上保形地形成第二电介质层; 在每个第一栅极结构的每个侧壁上形成具有比第二介电层更大的湿蚀刻速率的第一间隔物; 部分地去除第一和第二电介质层以暴露衬底。 在第一栅极结构之间的衬底上形成第三电介质层; 去除第一间隔物; 在所述第三介电层上形成第二导电层; 移除所述第一盖层和所述第一导电层的一部分以形成第二栅极结构; 以及在每个第二栅极结构的两侧在衬底中形成掺杂区域。

    Flash memory structure and method of making the same
    42.
    发明申请
    Flash memory structure and method of making the same 审中-公开
    闪存结构和制作方法相同

    公开(公告)号:US20080315284A1

    公开(公告)日:2008-12-25

    申请号:US11953886

    申请日:2007-12-11

    IPC分类号: H01L29/00 H01L21/336

    摘要: A flash memory cell includes a substrate, a T-shaped control gate disposed above the substrate, a floating gate embedded in a lower recess of the T-shaped control gate, a dielectric layer between the T-shaped control gate and the floating gate; a cap layer above the T-shaped control gate, a control gate oxide between the T-shaped control gate and the substrate, a floating gate oxide between the floating gate and the substrate, a liner covering the cap layer and the floating gate, and a source/drain region adjacent to the floating gate. The floating gate has a vertical wall surface that is coplanar with one side of the dielectric layer.

    摘要翻译: 闪存单元包括衬底,设置在衬底上方的T形控制栅极,嵌入在T形控制栅极的下凹槽中的浮置栅极,在T形控制栅极和浮置栅极之间的介电层; T形控制栅极上方的覆盖层,T形控制栅极和衬底之间的控制栅极氧化物,浮置栅极和衬底之间的浮置栅极氧化物,覆盖覆盖层和浮动栅极的衬底,以及 与浮动栅极相邻的源极/漏极区域。 浮动栅极具有与电介质层的一侧共面的垂直壁表面。

    SEMICONDUCTOR COMPONENT AND METHOD FOR FABRICATING THE SAME
    43.
    发明申请
    SEMICONDUCTOR COMPONENT AND METHOD FOR FABRICATING THE SAME 审中-公开
    半导体元件及其制造方法

    公开(公告)号:US20080296725A1

    公开(公告)日:2008-12-04

    申请号:US11955399

    申请日:2007-12-13

    IPC分类号: H01L23/00 H01L21/76

    摘要: A semiconductor component includes a substrate, two isolation structures, a conductor pattern and a dielectric layer. The isolation structures are disposed in the substrate, and each of the isolation structures has protruding portions protruding from the surface of the substrate. A trench is formed between the protruding portions. The included angle formed by the sidewall of the protruding portion and the surface of the substrate is an obtuse angle. The conductor pattern is disposed in the trench and fills the trench up. The dielectric layer is disposed between the conductor pattern and the substrate.

    摘要翻译: 半导体部件包括基板,两个隔离结构,导体图案和电介质层。 隔离结构设置在基板中,并且每个隔离结构具有从基板的表面突出的突出部分。 在突出部之间形成沟槽。 由突出部分的侧壁和基板的表面形成的夹角是钝角。 导体图案设置在沟槽中并将沟槽填满。 电介质层设置在导体图案和基板之间。

    Nonvolatile memory cell
    44.
    发明授权
    Nonvolatile memory cell 有权
    非易失性存储单元

    公开(公告)号:US08148766B2

    公开(公告)日:2012-04-03

    申请号:US12244295

    申请日:2008-10-02

    IPC分类号: H01L29/788

    摘要: A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting layer and the spacer layer. A first oxide layer is formed at the bottom of the trench. A dielectric layer is formed on the first oxide layer, the spacer layer and the plural side surfaces of the trench. A first polysilicon layer is formed in the trench. And a first portion of the dielectric layer on the spacer layer is removed, so that a basic structure for the nonvolatile memory cell is formed.

    摘要翻译: 提供非易失性存储单元。 提供半导体衬底。 导电层和间隔层顺序地设置在半导体衬底之上。 在导电层和间隔层中限定具有底部和多个侧表面的至少一个沟槽。 第一氧化物层形成在沟槽的底部。 在第一氧化物层,间隔层和沟槽的多个侧表面上形成介电层。 在沟槽中形成第一多晶硅层。 并且去除间隔层上的电介质层的第一部分,从而形成用于非易失性存储单元的基本结构。

    Method for manufacturing a memory
    45.
    发明授权
    Method for manufacturing a memory 有权
    存储器制造方法

    公开(公告)号:US07972924B2

    公开(公告)日:2011-07-05

    申请号:US12839387

    申请日:2010-07-19

    IPC分类号: H01L21/336

    CPC分类号: H01L27/11521

    摘要: A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer.

    摘要翻译: 一种用于制造存储器的方法,包括首先提供具有水平相邻的控制栅极区域和浮置栅极区域的衬底,该栅极区域包括牺牲层和牺牲侧壁,去除牺牲层和牺牲侧壁以露出衬底,形成邻近控制的电介质侧壁 栅极区域,在暴露的衬底上形成浮栅电介质层,并形成与电介质侧壁相邻的浮栅极和浮置栅极电介质层。

    Method for forming a semiconductor device
    46.
    发明授权
    Method for forming a semiconductor device 有权
    半导体器件形成方法

    公开(公告)号:US07855124B2

    公开(公告)日:2010-12-21

    申请号:US12035529

    申请日:2008-02-22

    IPC分类号: H01L21/76

    摘要: A method for forming a semiconductor device, includes the steps of providing a substrate; forming a patterned stack on the substrate including a first dielectric layer on the substrate, a first conductive layer on the first dielectric layer and a mask layer on the first conductive layer, wherein a width of the mask layer is smaller than a width of the first conductive layer; forming a second dielectric layer on the sidewall of the patterned stack; forming a third dielectric layer on the substrate; forming a second conductive layer over the substrate; and removing the mask layer and a portion of the first conductive layer covered by the mask layer to form an opening so as to partially expose the first conductive layer.

    摘要翻译: 一种形成半导体器件的方法,包括以下步骤:提供衬底; 在所述衬底上形成图案化的叠层,所述衬底上包括在所述衬底上的第一电介质层,所述第一电介质层上的第一导电层和所述第一导电层上的掩模层,其中所述掩模层的宽度小于所述第一导电层的宽度 导电层; 在所述图案化叠层的侧壁上形成第二电介质层; 在所述基板上形成第三电介质层; 在所述衬底上形成第二导电层; 以及去除所述掩模层和由所述掩模层覆盖的所述第一导电层的一部分以形成开口以部分地暴露所述第一导电层。

    METHOD FOR MANUFACTURING A MEMORY
    47.
    发明申请
    METHOD FOR MANUFACTURING A MEMORY 有权
    制造存储器的方法

    公开(公告)号:US20100279499A1

    公开(公告)日:2010-11-04

    申请号:US12839387

    申请日:2010-07-19

    IPC分类号: H01L21/8247

    CPC分类号: H01L27/11521

    摘要: A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer.

    摘要翻译: 一种用于制造存储器的方法,包括首先提供具有水平相邻的控制栅极区域和浮置栅极区域的衬底,该栅极区域包括牺牲层和牺牲侧壁,去除牺牲层和牺牲侧壁以露出衬底,形成邻近控制的电介质侧壁 栅极区域,在暴露的衬底上形成浮栅电介质层,并形成与电介质侧壁相邻的浮栅极和浮置栅极电介质层。

    Non-volatile memory
    48.
    发明授权
    Non-volatile memory 有权
    非易失性存储器

    公开(公告)号:US07781804B2

    公开(公告)日:2010-08-24

    申请号:US12101164

    申请日:2008-04-11

    IPC分类号: H01L29/80

    摘要: A non-volatile memory disposed on a substrate includes active regions, a memory array, and contacts. The active regions defined by isolation structures disposed in the substrate are extended in a first direction. The memory array is disposed on the substrate and includes memory cell columns, control gate lines and select gate lines. Each of the memory cell columns includes memory cells connected to one another in series and a source/drain region disposed in the substrate outside the memory cells. The contacts are disposed on the substrate at a side of the memory array and arranged along a second direction. The second direction crosses over the first direction. Each of the contacts extends across the isolation structures and connects the source/drain regions in the substrate at every two of the adjacent active regions.

    摘要翻译: 设置在基板上的非易失性存储器包括有源区,存储器阵列和触点。 由设置在基板中的隔离结构限定的有源区域沿第一方向延伸。 存储器阵列设置在衬底上,并且包括存储单元列,控制栅极线和选择栅极线。 每个存储单元列包括彼此串联的存储单元和设置在存储单元外部的衬底中的源/漏区。 触点在存储器阵列的一侧设置在衬底上,并沿第二方向布置。 第二个方向穿过第一个方向。 每个触点延伸穿过隔离结构,并且在每个相邻的活性区域的每两个处连接衬底中的源极/漏极区域。

    NONVOLATILE MEMORY CELL
    49.
    发明申请
    NONVOLATILE MEMORY CELL 有权
    非易失性存储单元

    公开(公告)号:US20100013062A1

    公开(公告)日:2010-01-21

    申请号:US12244295

    申请日:2008-10-02

    IPC分类号: H01L23/58 H01L21/31

    摘要: A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting layer and the spacer layer. A first oxide layer is formed at the bottom of the trench. A dielectric layer is formed on the first oxide layer, the spacer layer and the plural side surfaces of the trench. A first polysilicon layer is formed in the trench. And a first portion of the dielectric layer on the spacer layer is removed, so that a basic structure for the nonvolatile memory cell is formed.

    摘要翻译: 提供非易失性存储单元。 提供半导体衬底。 导电层和间隔层顺序地设置在半导体衬底之上。 在导电层和间隔层中限定具有底部和多个侧表面的至少一个沟槽。 第一氧化物层形成在沟槽的底部。 在第一氧化物层,间隔层和沟槽的多个侧表面上形成介电层。 在沟槽中形成第一多晶硅层。 并且去除间隔层上的电介质层的第一部分,从而形成用于非易失性存储单元的基本结构。

    METHOD FOR MANUFACTURING TRENCH ISOLATION STRUCTURE AND NON-VOLATILE MEMORY
    50.
    发明申请
    METHOD FOR MANUFACTURING TRENCH ISOLATION STRUCTURE AND NON-VOLATILE MEMORY 有权
    制造分离结构和非易失性存储器的方法

    公开(公告)号:US20090061581A1

    公开(公告)日:2009-03-05

    申请号:US11945199

    申请日:2007-11-26

    IPC分类号: H01L21/336

    摘要: A method for manufacturing a non-volatile memory is provided. An isolation structure is formed in a trench formed in a substrate. A portion of the isolation structure is removed to form a recess. A first dielectric layer and a first conductive layer are formed sequentially on the substrate. Bar-shaped cap layers are formed on the substrate. The first conductive layer not covered by the bar-shaped cap layers is removed to form first gate structures. A second dielectric layer is formed on the sidewalls of the first gate structures. A third dielectric layer is formed on the substrate between the first gate structures. A second conductive layer is formed on the third dielectric layer. The bar-shaped cap layers and a portion of the first conductive layer are removed to form second gate structures. A doped region is formed in the substrate at two sides of each of the second gate structures.

    摘要翻译: 提供一种用于制造非易失性存储器的方法。 在衬底中形成的沟槽中形成隔离结构。 去除隔离结构的一部分以形成凹部。 在基板上依次形成第一介电层和第一导电层。 在基板上形成棒状盖层。 未被棒状帽层覆盖的第一导电层被去除以形成第一栅极结构。 在第一栅极结构的侧壁上形成第二介电层。 在第一栅极结构之间的衬底上形成第三电介质层。 在第三电介质层上形成第二导电层。 条形盖层和第一导电层的一部分被去除以形成第二栅极结构。 在每个第二栅极结构的两侧在衬底中形成掺杂区域。