公开(公告)号：US20180151581A1

公开(公告)日：2018-05-31

申请号：US15428823

申请日：2017-02-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Wei Cheng WU ,  Li-Feng TENG

IPC分类号： H01L27/11531 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L27/11531 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11541 ,  H01L27/11543 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66545

摘要： A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

公开(公告)号：US09972633B2

公开(公告)日：2018-05-15

申请号：US15008185

申请日：2016-01-27

申请人： United Microelectronics Corp.

发明人： Hui Yang ,  Chow-Yee Lim

IPC分类号： H01L29/788 ,  H01L27/11534 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/51 ,  H01L29/45 ,  H01L21/02

CPC分类号： H01L27/11534 ,  H01L21/02164 ,  H01L21/0217 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11541 ,  H01L27/11543 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/45 ,  H01L29/513 ,  H01L29/518

摘要： A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.

公开(公告)号：US20170213839A1

公开(公告)日：2017-07-27

申请号：US15008185

申请日：2016-01-27

申请人： United Microelectronics Corp.

发明人： Hui Yang ,  Chow-Yee Lim

IPC分类号： H01L27/115 ,  H01L29/45 ,  H01L21/02 ,  H01L29/51

CPC分类号： H01L27/11534 ,  H01L21/02164 ,  H01L21/0217 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11541 ,  H01L27/11543 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/45 ,  H01L29/513 ,  H01L29/518

摘要： A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.

公开(公告)号：US20170103991A1

公开(公告)日：2017-04-13

申请号：US15264457

申请日：2016-09-13

申请人： Silicon Storage Technology, Inc.

发明人： JINHO KIM ,  CHIEN-SHENG SU ,  FENG ZHOU ,  XIAN LIU ,  NHAN DO ,  PRATEEP TUNTASOOD ,  PARVIZ GHAZAVI

IPC分类号： H01L27/115

CPC分类号： H01L27/11531 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543

摘要： A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas.

公开(公告)号：US09466605B2

公开(公告)日：2016-10-11

申请号：US14601232

申请日：2015-01-21

申请人： Powerchip Technology Corporation

发明人： Kai-Yao Shih ,  Ssu-Ting Wang ,  Chi-Kai Feng ,  Tzung-Hua Ying ,  Te-Yuan Yin

IPC分类号： H01L21/311 ,  H01L21/266 ,  H01L27/115 ,  H01L21/265 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L27/11548 ,  H01L21/265 ,  H01L21/266 ,  H01L21/31111 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11543 ,  H01L29/401 ,  H01L29/6656 ,  H01L29/66825

摘要： A method of manufacturing a non-volatile memory is provided. A substrate including a first region and a second region is provided. A first patterning process is performed to the first region, so as to form a plurality of gate stack structures in the first region. Afterwards, a first sidewall oxide layer is formed to cover sidewalls and an upper surface of each gate stack structure, and a protection layer is then formed on the first sidewall oxide layer. Next, an ion implantation process is performed to the second region, and a second patterning process is performed to the second region so as to form a plurality of gate structures. Then, a second sidewall oxide layer covering sidewalls of each gate structure is formed.

摘要翻译： 提供一种制造非易失性存储器的方法。 提供了包括第一区域和第二区域的衬底。 对第一区域执行第一图案化处理，以便在第一区域中形成多个栅叠层结构。 然后，形成第一侧壁氧化物层以覆盖每个栅极堆叠结构的侧壁和上表面，然后在第一侧壁氧化物层上形成保护层。 接下来，对第二区域进行离子注入处理，并且对第二区域进行第二图案化处理，以形成多个栅极结构。 然后，形成覆盖每个栅极结构的侧壁的第二侧壁氧化物层。

公开(公告)号：US09431503B2

公开(公告)日：2016-08-30

申请号：US14149521

申请日：2014-01-07

申请人： Cypress Semiconductor Corporation

发明人： Chuan Lin ,  Hidehiko Shiraiwa ,  Bradley Marc Davis ,  Lei Xue ,  Simon S. Chan ,  Kenichi Ohtsuka ,  Angela T. Hui ,  Scott Allan Bell

IPC分类号： H01L29/49 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/115 ,  H01L21/28

CPC分类号： H01L29/4916 ,  H01L21/28044 ,  H01L21/823456 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/78

摘要： An integrated circuit comprises a first poly-silicon region including a first poly-silicon layer, a second poly-silicon layer disposed over the first poly-silicon layer, a first poly-silicon finger associated with the first poly-silicon layer, and a second poly-silicon finger associated with the second poly-silicon layer. The first poly-silicon finger and the second poly-silicon finger are oriented in a substantially orthogonal manner relative to each other. The integrated circuit comprises a second poly-silicon gate region including the first poly-silicon layer. The first polysilicon gate region and the second polysilicon gate region each have different poly-silicon gate structures.

摘要翻译： 集成电路包括第一多晶硅区域，第一多晶硅区域包括第一多晶硅层，设置在第一多晶硅层上的第二多晶硅层，与第一多晶硅层相关联的第一多硅指状物，以及 与第二多晶硅层相关联的第二多硅指状物。 第一多硅指状物和第二多晶硅指状物相对于彼此以基本上正交的方式取向。 集成电路包括包括第一多晶硅层的第二多晶硅栅极区域。 第一多晶硅栅极区域和第二多晶硅栅极区域各自具有不同的多晶硅栅极结构。

公开(公告)号：US20160233228A1

公开(公告)日：2016-08-11

申请号：US14645993

申请日：2015-03-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Chien-Hung Chang

IPC分类号： H01L27/115 ,  H01L29/51 ,  H01L21/28 ,  H01L49/02

CPC分类号： H01L21/28273 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/42328 ,  H01L29/42332

摘要： The present disclosure relates to a non-planar FEOL (front-end-of-the-line) capacitor comprising a charge trapping dielectric layer disposed between electrodes, and an associated method of fabrication. In some embodiments, the non-planar FEOL capacitor has a first electrode disposed over a substrate. A charge trapping dielectric layer is disposed onto the substrate at a position adjacent to the first electrode. The charge trapping dielectric layer has an “L” shape, with a lateral component extending in a first direction and a vertical component extending in a second direction. A second electrode is arranged onto the lateral component and is separated from the first electrode by the first component.

摘要翻译： 本公开涉及一种包括设置在电极之间的电荷捕获介电层的非平面FEOL（前端线）电容器和相关的制造方法。 在一些实施例中，非平面FEOL电容器具有设置在衬底上的第一电极。 电荷捕获电介质层在与第一电极相邻的位置处设置在基板上。 电荷俘获介电层具有“L”形状，其中侧向分量沿第一方向延伸，垂直分量沿第二方向延伸。 第二电极布置在侧向部件上并且通过第一部件与第一电极分离。

公开(公告)号：US20160190148A1

公开(公告)日：2016-06-30

申请号：US14961525

申请日：2015-12-07

申请人： Semiconductor Manufacturing International (Shanghai) Corporation

发明人： YiPeng CHAN ,  Jieqiong DONG ,  Huajun JIN ,  Ruling ZHOU ,  Shibi GUO ,  Bongkil KIM

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/66

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

摘要： A method for manufacturing a semiconductor device includes providing a substrate, a first conductor, a second conductor, a first dielectric, a second dielectric, and a designated region. The first conductor is positioned between the first dielectric and the substrate. The second conductor is positioned between the second dielectric and the substrate. The first designated region is positioned in the substrate. The method includes providing a conductive material layer, which completely covers the first dielectric and the second dielectric. The method includes partially removing the conductive material layer to form a third conductor and a fourth conductor. The first dielectric is positioned between the third conductor and the first conductor. The fourth conductor directly contacts the designated region. The method includes implementing a memory unit using the first conductor and the third conductor and includes implementing a logic unit using the second conductor and the designated region.

摘要翻译： 一种制造半导体器件的方法包括提供衬底，第一导体，第二导​​体，第一电介质，第二电介质和指定区域。 第一导体位于第一电介质和衬底之间。 第二导体位于第二电介质和衬底之间。 第一指定区域位于基板中。 该方法包括提供完全覆盖第一电介质和第二电介质的导电材料层。 该方法包括部分去除导电材料层以形成第三导体和第四导体。 第一电介质位于第三导体和第一导体之间。 第四根导体直接接触指定区域。 该方法包括使用第一导体和第三导体实现存储器单元，并且包括使用第二导体和指定区域实现逻辑单元。

公开(公告)号：US09373513B2

公开(公告)日：2016-06-21

申请号：US14863931

申请日：2015-09-24

申请人： Samsung Electronics Co., Ltd.

发明人： HyoJoong Kim ,  ByeongHoon Kim ,  In-Young Kim ,  Sang Bong Shin ,  Songha Oh

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115 ,  H01L21/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/3215 ,  H01L21/762

CPC分类号： H01L21/28273 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/32155 ,  H01L21/76224 ,  H01L27/11529 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/7881

摘要： A semiconductor device includes a substrate including an active region defined by a device isolation pattern and a floating gate on the active region. The floating gate includes an upper portion, a lower portion having a width greater than a width of the upper portion, and a step-difference portion between the upper portion and the lower portion. A dielectric pattern is on the floating gate, and a control gate is on the dielectric pattern. The lower portion of the floating gate has a height of about 4 nm or more.

摘要翻译： 半导体器件包括：衬底，其包括由器件隔离图案限定的有源区和有源区上的浮置栅。 浮动门包括上部，具有大于上部宽度的宽度的下部，以及上部和下部之间的台阶差部分。 电介质图案位于浮动栅极上，控制栅极位于电介质图案上。 浮栅的下部具有约4​​nm或更大的高度。

公开(公告)号：US09343465B2

公开(公告)日：2016-05-17

申请号：US14472496

申请日：2014-08-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Liang Chu ,  Ruey-Hsin Liu ,  Chih-Wen Albert Yao ,  Ming-Ta Lei

IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/28 ,  H01L21/02 ,  H01L21/265

CPC分类号： H01L27/11521 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28273 ,  H01L27/11526 ,  H01L27/11543 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7883

摘要： Some embodiments of the present disclosure are directed to an embedded flash (e-flash) memory device that includes a flash memory cell and a metal-oxide-semiconductor field-effect transistor (MOSFET). The flash memory cell includes a control gate disposed over a floating gate. The MOSFET includes a logic gate disposed over a gate dielectric. The floating gate and a first gate layer of the logic gate are simultaneously formed with a first polysilicon layer. A high temperature oxide (HTO) is then formed over the floating gate with a high temperature process, while the first gate layer protects the gate dielectric from degradation effects due to the high temperature process. A second gate layer of the logic gate is then formed over the first gate layer by a second polysilicon layer. The first and second gate layers collectively form a logic gate of the MOSFET.

摘要翻译： 本公开的一些实施例涉及包括闪存单元和金属氧化物半导体场效应晶体管（MOSFET）的嵌入式闪存（e-flash）存储器件。 闪存单元包括设置在浮动栅极上的控制栅极。 MOSFET包括设置在栅极电介质上的逻辑门。 逻辑门的浮置栅极和第一栅极层同时形成有第一多晶硅层。 然后，通过高温工艺在浮栅上形成高温氧化物（HTO），而第一栅极层由于高温处理而保护栅极电介质免受劣化影响。 然后通过第二多晶硅层在第一栅极层上形成逻辑门的第二栅极层。 第一和第二栅极层共同形成MOSFET的逻辑门。