公开(公告)号：US07855124B2

公开(公告)日：2010-12-21

申请号：US12035529

申请日：2008-02-22

申请人： Hung-Ming Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Hung-Ming Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L21/76

CPC分类号： H01L21/823437 ,  H01L21/28273 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/11521

摘要： A method for forming a semiconductor device, includes the steps of providing a substrate; forming a patterned stack on the substrate including a first dielectric layer on the substrate, a first conductive layer on the first dielectric layer and a mask layer on the first conductive layer, wherein a width of the mask layer is smaller than a width of the first conductive layer; forming a second dielectric layer on the sidewall of the patterned stack; forming a third dielectric layer on the substrate; forming a second conductive layer over the substrate; and removing the mask layer and a portion of the first conductive layer covered by the mask layer to form an opening so as to partially expose the first conductive layer.

摘要翻译： 一种形成半导体器件的方法，包括以下步骤：提供衬底; 在所述衬底上形成图案化的叠层，所述衬底上包括在所述衬底上的第一电介质层，所述第一电介质层上的第一导电层和所述第一导电层上的掩模层，其中所述掩模层的宽度小于所述第一导电层的宽度 导电层; 在所述图案化叠层的侧壁上形成第二电介质层; 在所述基板上形成第三电介质层; 在所述衬底上形成第二导电层; 以及去除所述掩模层和由所述掩模层覆盖的所述第一导电层的一部分以形成开口以部分地暴露所述第一导电层。

公开(公告)号：US07868377B2

公开(公告)日：2011-01-11

申请号：US11927616

申请日：2007-10-29

申请人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L29/94

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the space between the gate conductor lines, which are for interconnecting the select gates of the select gate transistors arranged on the same column, can be shortened. Therefore, the integration of the flash memory can be increased; and the process window of the STI process can be increased as well. In addition, at least one depletion-mode select gate transistor is at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.

摘要翻译： 提供闪存。 具有选择栅极晶体管的闪存特征包括两个不同的沟道结构，它们是凹陷沟道结构和水平沟道。 由于凹陷沟道结构的设计，可以缩短用于互连布置在同一列上的选择栅晶体管的选通栅极的栅极导体线之间的空间。 因此，可以增加闪存的集成; 并且可以增加STI过程的处理窗口。 此外，至少一个耗尽型选择栅极晶体管位于存储单元串的一侧。 耗尽模式的选择栅晶体管总是导通。

公开(公告)号：US07682902B2

公开(公告)日：2010-03-23

申请号：US11949786

申请日：2007-12-04

申请人： Ching-Nan Hsiao ,  Pei-Ing Lee ,  Ming-Cheng Chang ,  Chung-Lin Huang ,  Hsi-Hua Chang ,  Chih-Hsiang Wu

发明人： Ching-Nan Hsiao ,  Pei-Ing Lee ,  Ming-Cheng Chang ,  Chung-Lin Huang ,  Hsi-Hua Chang ,  Chih-Hsiang Wu

IPC分类号： H01L21/336

CPC分类号： H01L27/11534 ,  H01L21/84 ,  H01L27/11526 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7887

摘要： A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the first recessed trench. A first conductive layer is formed on the first gate dielectric layer. After that, the first conductive layer is etched to form a spacer which functions as a floating gate on a sidewall of the first recessed trench. A second recessed trench is formed in a bottom of the first recessed trench. An inter-gate dielectric layer is formed on a surface of the spacer, a sidewall and a bottom of the second recessed trench. A second conductive layer formed to fill up the first and the second recessed trench.

摘要翻译： 本发明公开的存储器结构的特征在于控制栅极和位于凹槽中的浮栅。 一种制造存储器结构的方法包括以下步骤：首先提供具有第一凹槽的衬底。 然后，在第一凹槽上形成第一栅极电介质层。 第一导电层形成在第一栅极介电层上。 之后，蚀刻第一导电层以形成用作第一凹槽的侧壁上的浮动栅极的间隔物。 在第一凹槽的底部形成第二凹槽。 在间隔物的表面，第二凹槽的侧壁和底部上形成栅极间电介质层。 形成为填充第一和第二凹槽的第二导电层。

公开(公告)号：US08330198B2

公开(公告)日：2012-12-11

申请号：US12758252

申请日：2010-04-12

申请人： Shin Bin Huang ,  Chung-Lin Huang ,  Ching-Nan Hsiao ,  Tzung Han Lee

发明人： Shin Bin Huang ,  Chung-Lin Huang ,  Ching-Nan Hsiao ,  Tzung Han Lee

IPC分类号： H01L27/108

CPC分类号： H01L27/0259

摘要： A device for preventing current-leakage is located between a transistor and a capacitor of a memory cell. The two terminals of the device for preventing current-leakage are respectively connected with a slave terminal of the transistor and an electric pole of the capacitor. The device for preventing current-leakage has at least two p-n junctions. The device for preventing current-leakage is a lateral silicon controlled rectifier, a diode for alternating current, or a silicon controlled rectifier. By utilizing the driving characteristic of the device for preventing current-leakage, electric charge stored in the capacitor hardly passes through the device for preventing current-leakage when the transistor is turned off to improve the current-leakage problem.

摘要翻译： 用于防止漏电的装置位于存储单元的晶体管和电容器之间。 用于防止漏电的装置的两个端子分别与晶体管的从端和电容器的电极连接。 用于防止漏电的装置具有至少两个p-n结。 用于防止漏电的装置是侧向可控硅整流器，用于交流电流的二极管或可控硅整流器。 通过利用用于防止漏电的装置的驱动特性，存储在电容器中的电荷几乎不会通过用于防止晶体管截止时漏电的装置，从而改善漏电问题。

公开(公告)号：US07981743B2

公开(公告)日：2011-07-19

申请号：US12039744

申请日：2008-02-29

申请人： Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L21/336 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11568

摘要： The memory cell of the present invention has two independent storage regions embedded into two opposite sidewalls of the control gate respectively. In this way, the data storage can be more reliable. Other features of the present invention are that the thickness of the dielectric layers is different, and the two independent storage regions are formed on opposite bottom sides of the opening by the etching process and form a shape like a spacer. The advantage of the aforementioned method is that the fabricating process is simplified and the difficulty of self-alignment is reduced.

摘要翻译： 本发明的存储单元具有分别嵌入控制门的两个相对的侧壁中的两个独立的存储区域。 以这种方式，数据存储可以更可靠。 本发明的其他特征是电介质层的厚度不同，并且两个独立的存储区域通过蚀刻工艺形成在开口的相对的底侧上并形成像间隔物的形状。 上述方法的优点是简化了制造工艺，并且减少了自对准的难度。

公开(公告)号：US20100279472A1

公开(公告)日：2010-11-04

申请号：US12838495

申请日：2010-07-19

申请人： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L21/8239

CPC分类号： H01L27/115 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： In a manufacturing method of a non-volatile memory, a substrate is provided, and strip-shaped isolation structures are formed in the substrate. A first memory array including memory cell columns is formed on the substrate. Each memory cell column includes memory cells connected in series with one another, a source/drain region disposed in the substrate outside the memory cells, select transistors disposed between the source/drain region and the memory cells, control gate lines extending across the memory cell columns and in a second direction, and first select gate lines respectively connecting the select transistors in the second direction in series. First contacts are formed on the substrate at a side of the first memory array and arranged along the second direction. Each first contact connects the source/drain regions in every two adjacent active regions.

摘要翻译： 在非易失性存储器的制造方法中，提供衬底，并且在衬底中形成条形隔离结构。 包括存储单元列的第一存储器阵列形成在衬底上。 每个存储单元列包括彼此串联连接的存储器单元，设置在存储单元外部的衬底中的源极/漏极区域，设置在源极/漏极区域和存储器单元之间的选择晶体管，跨过存储器单元延伸的控制栅极线 列和第二方向，并且首先选择分别连接第二方向上的选择晶体管的栅极线。 第一触点形成在第一存储器阵列的一侧的基板上，并沿第二方向布置。 每个第一接触件在每两个相邻有效区域中连接源极/漏极区域。

公开(公告)号：US07713820B2

公开(公告)日：2010-05-11

申请号：US11945199

申请日：2007-11-26

申请人： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： A method for manufacturing a non-volatile memory is provided. An isolation structure is formed in a trench formed in a substrate. A portion of the isolation structure is removed to form a recess. A first dielectric layer and a first conductive layer are formed sequentially on the substrate. Bar-shaped cap layers are formed on the substrate. The first conductive layer not covered by the bar-shaped cap layers is removed to form first gate structures. A second dielectric layer is formed on the sidewalls of the first gate structures. A third dielectric layer is formed on the substrate between the first gate structures. A second conductive layer is formed on the third dielectric layer. The bar-shaped cap layers and a portion of the first conductive layer are removed to form second gate structures. A doped region is formed in the substrate at two sides of each of the second gate structures.

摘要翻译： 提供一种用于制造非易失性存储器的方法。 在衬底中形成的沟槽中形成隔离结构。 去除隔离结构的一部分以形成凹部。 在基板上依次形成第一介电层和第一导电层。 在基板上形成棒状盖层。 未被棒状帽层覆盖的第一导电层被去除以形成第一栅极结构。 在第一栅极结构的侧壁上形成第二介电层。 在第一栅极结构之间的衬底上形成第三电介质层。 在第三电介质层上形成第二导电层。 条形盖层和第一导电层的一部分被去除以形成第二栅极结构。 在每个第二栅极结构的两侧在衬底中形成掺杂区域。

公开(公告)号：US20090032858A1

公开(公告)日：2009-02-05

申请号：US11927616

申请日：2007-10-29

申请人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the space between the gate conductor lines, which are for interconnecting the select gates of the select gate transistors arranged on the same column, can be shortened. Therefore, the integration of the flash memory can be increased; and the process window of the STI process can be increased as well. In addition, at least one depletion-mode select gate transistor is at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.

摘要翻译： 提供闪存。 具有选择栅极晶体管的闪存特征包括两个不同的沟道结构，它们是凹陷沟道结构和水平沟道。 由于凹陷沟道结构的设计，可以缩短用于互连布置在同一列上的选择栅极晶体管的选择栅极的栅极导体线之间的空间。 因此，可以增加闪存的集成; 并且可以增加STI过程的处理窗口。 此外，至少一个耗尽型选择栅极晶体管位于存储单元串的一侧。 耗尽模式的选择栅晶体管总是导通。

公开(公告)号：US08105900B2

公开(公告)日：2012-01-31

申请号：US12838495

申请日：2010-07-19

申请人： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： In a manufacturing method of a non-volatile memory, a substrate is provided, and strip-shaped isolation structures are formed in the substrate. A first memory array including memory cell columns is formed on the substrate. Each memory cell column includes memory cells connected in series with one another, a source/drain region disposed in the substrate outside the memory cells, select transistors disposed between the source/drain region and the memory cells, control gate lines extending across the memory cell columns and in a second direction, and first select gate lines respectively connecting the select transistors in the second direction in series. First contacts are formed on the substrate at a side of the first memory array and arranged along the second direction. Each first contact connects the source/drain regions in every two adjacent active regions.

摘要翻译： 在非易失性存储器的制造方法中，提供衬底，并且在衬底中形成条形隔离结构。 包括存储单元列的第一存储器阵列形成在衬底上。 每个存储单元列包括彼此串联连接的存储器单元，设置在存储单元外部的衬底中的源极/漏极区域，设置在源极/漏极区域和存储器单元之间的选择晶体管，跨越存储器单元延伸的控制栅极线 列和第二方向，并且首先选择分别连接第二方向上的选择晶体管的栅极线。 第一触点形成在第一存储器阵列的一侧的基板上，并沿第二方向布置。 每个第一接触件在每两个相邻有效区域中连接源极/漏极区域。

公开(公告)号：US07714445B2

公开(公告)日：2010-05-11

申请号：US11951274

申请日：2007-12-05

申请人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

发明人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC分类号： H01L23/552 ,  H01L21/768

CPC分类号： H01L27/0251 ,  H01L27/10894

摘要： The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin.

摘要翻译： 本发明提供一种具有静电放电（ESD）区域的动态随机存取存储器（DRAM）。 ESD插头的上部是金属，ESD插头的下部是多晶硅。 该结构可以提高ESD区域的机械强度并增强静电放电的导热性。 此外，可以减少ESD插头和基板之间的接触面积，而不增加ESD插头的纵横比。 所描述的结构由低临界尺寸控制的图案化光致抗蚀剂完成，使得工艺和设备基本上保持而不会大幅变化。