Abstract:
Various embodiments herein include one or more of systems, methods, software, and/or data structures to determine voltage margin for a high-speed serial data link. Advantageously, the margin determination may be made during normal operation of the data link (“mission mode”) such that the performance of the data link is not affected by the voltage margin measurements. That is, the margin measurements may be performed “on line” rather than “off line.” To facilitate the voltage margin measurement, a plurality of digital samples from an analog to digital converter (ADC) may be evaluated to determine the most probable bit values (i.e., digital 1's and 0's) that are represented by the digital samples. Then, a method may be used to remove or compensate for ISI effects from one or more of the digital samples, thereby providing an accurate representation of the voltage margin present in a data link. Subsequently, the voltage margin may be periodically monitored over time to detect degradation of the data link.
Abstract:
An linear equalizer system for a transmission channel includes an active inductor with a tunable inductance and quality factor. The active inductor includes a transconducting element. A current steering digital to analog converter controls the flow of a bias current through the transconducting element to tune the active inductor.
Abstract:
An apparatus and method are provided to enable an adaptation unit to be shared among a plurality of receivers. The adaptation unit provides compensation values to each receiver to enable each receiver to compensate for the pulse response effect experienced by that receiver. By sharing an adaptation unit among a plurality of receivers rather than having a dedicated adaptation unit for each receiver, the chip space needed is significantly reduced since the number of adaptation units that need to be implemented is significantly reduced. In addition, the fewer number of adaptation units leads to less power consumption during operation. Overall, the sharing of the adaptation unit enables greater efficiency and improved scalability to be achieved.
Abstract:
A two stage fully differential amplifier has been designed which works, in tandem with a TX-FIR, as a linear equalizer at low frequencies, not covered by the TX-FIR, and also acts as a linear amplifier at higher frequencies which are equalized by the TX-FIR. The amplifier as a frequency response which does not attenuate signals frequencies less than one twentieth of baud rate, creates gain peaking ion the region between one twentieth and one tenth of baud rate and maintains flat peak gain up to half of baud rate. Different aspects of the frequency response curve (such as dc gain, max gain and zero frequency) are completely programmable. Also, the differential amplifier has been designed from low power and process, voltage and temperature insensitive frequency response.
Abstract:
A feedback module is defined to receive as input a set of data sample signals and a set of reference sample signals. Each of the data and reference sample signals is generated by sampling a differential signal having been transmitted through a FIR filter. The feedback module is defined to operate a respective post cursor counter for each post cursor of the FIR filter and update the post cursor counters based on the received sets of data and reference sample signals. Also, the feedback module is defined to generate a tap weight adjustment signal for a given tap weight of the FIR filter when a magnitude of a post cursor counter corresponding to the given tap weight is greater than or equal to a threshold value. An adaptation module is defined to adapt a reference voltage used to generate the reference sample signals to a condition of the differential signal.
Abstract:
An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.
Abstract:
An linear equalizer system for a transmission channel includes an active inductor with a tunable inductance and quality factor. The active inductor includes a transconducting element. A current steering digital to analog converter controls the flow of a bias current through the transconducting element to tune the active inductor.
Abstract:
A method and system forwards voice messages from a sender to a receiver through a network. A voice-mail device records a phone number of a receiver and a voice message of a sender within a digital file. The voice message and phone number are encapsulated within an e-mail, which is forwarded through a network to another voice-mail device that acts as a gateway. The e-mail is opened to obtain the phone number of the receiver and the voice message, and the phone number of the receiver is dialed to deliver the voice message to the receiver via a telephone network.
Abstract:
The present invention provides methods for reconstructing lost or corrupted packets. One embodiment of the method may include performing at least one parity operation on information associated with at least one first packet. The method may also include transmitting the information associated with at least one first packet and information indicative of the at least one parity operation. Another embodiment of the method may include accessing information associated with at least one first packet and information indicative of at least one parity operation performed on information associated with at least one first packet and at least one second packet. The method may also include determining information associated with the at least one second packet based on information associated with at least one first packet and information indicative of at least one parity operation performed on information associated with at least one first packet and the least one second packet.