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45 条记录 (耗时 0.033 秒)

    Capacitor Pairs with Improved Mismatch Performance
    41.
    发明申请
    Capacitor Pairs with Improved Mismatch Performance 有权
    具有改进的不匹配性能的电容对

    公开(公告)号：US20090212392A1

    公开(公告)日：2009-08-27

    申请号：US12463949

    申请日：2009-05-11

    申请人： Chia-Yi Chen ,  Chung-Long Chang ,  Chih-Ping Chao

    发明人： Chia-Yi Chen ,  Chung-Long Chang ,  Chih-Ping Chao

    IPC分类号： H01L29/92

    CPC分类号： H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first capacitor comprising a plurality of first unit capacitors interconnected to each other, each having a first unit capacitance; and a second capacitor comprising a plurality of second unit capacitors interconnected to each other, each having a second unit capacitance, wherein the first unit capacitors and the second unit capacitors have equal numbers of unit capacitors. The first unit capacitors and the second unit capacitors are arranged in an array with rows and columns and placed in an alternating pattern in each row and each column. The first and the second unit capacitors each have a total number greater than two.

    摘要翻译： 半导体器件包括：第一电容器，包括彼此互连的多个第一单位电容器，每个具有第一单位电容; 以及包括彼此互连的多个第二单位电容器的第二电容器，每个具有第二单位电容，其中所述第一单位电容器和所述第二单位电容器具有相等数目的单位电容器。 第一单元电容器和第二单元电容器以具有行和列的阵列排列并且以每行和每列置于交替图案中。 第一和第二单元电容器的总数大于2。

    Capacitor pairs with improved mismatch performance
    42.
    发明授权
    Capacitor pairs with improved mismatch performance 有权
    具有改善失配性能的电容对

    公开(公告)号：US07545022B2

    公开(公告)日：2009-06-09

    申请号：US11591644

    申请日：2006-11-01

    申请人： Chia-Yi Chen ,  Chung-Long Chang ,  Chih-Ping Chao

    发明人： Chia-Yi Chen ,  Chung-Long Chang ,  Chih-Ping Chao

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first capacitor comprising a plurality of first unit capacitors interconnected to each other, each having a first unit capacitance; and a second capacitor comprising a plurality of second unit capacitors interconnected to each other, each having a second unit capacitance, wherein the first unit capacitors and the second unit capacitors have equal numbers of unit capacitors. The first unit capacitors and the second unit capacitors are arranged in an array with rows and columns and placed in an alternating pattern in each row and each column. The first and the second unit capacitors each have a total number greater than two.

    摘要翻译： 半导体器件包括：第一电容器，包括彼此互连的多个第一单位电容器，每个具有第一单位电容; 以及包括彼此互连的多个第二单位电容器的第二电容器，每个具有第二单位电容，其中所述第一单位电容器和所述第二单位电容器具有相等数目的单位电容器。 第一单元电容器和第二单元电容器以具有行和列的阵列排列并且以每行和每列置于交替图案中。 第一和第二单元电容器的总数大于2。

    METHODS FOR FORMING CAPACITOR STRUCTURES
    43.
    发明申请
    METHODS FOR FORMING CAPACITOR STRUCTURES 有权
    形成电容器结构的方法

    公开(公告)号：US20080299723A1

    公开(公告)日：2008-12-04

    申请号：US11757763

    申请日：2007-06-04

    申请人： C. C. Wu ,  Chi-Feng Huang ,  Chun-Hung Chen ,  Chih-Ping Chao ,  John Chern

    发明人： C. C. Wu ,  Chi-Feng Huang ,  Chun-Hung Chen ,  Chih-Ping Chao ,  John Chern

    IPC分类号： H01L21/82

    CPC分类号： H01L27/0629 ,  H01L29/7833

    摘要： A method for forming a capacitor includes forming a dielectric layer over a substrate. A conductive layer is formed over the dielectric layer. Dopants are implanted through at least one of the dielectric layer and the conductive layer after forming the dielectric layer so as to form a conductive region under the dielectric layer, wherein the conductive layer is a top electrode of the capacitor and the conductive region is a bottom electrode of the capacitor.

    摘要翻译： 形成电容器的方法包括在衬底上形成电介质层。 在电介质层上形成导电层。 在形成电介质层之后，通过介电层和导电层中的至少一个注入掺杂剂，以在电介质层下方形成导电区域，其中导电层是电容器的顶部电极，导电区域是底部 电容器的电极。

    Forming reverse-extension MOS in standard CMOS flow
    44.
    发明申请
    Forming reverse-extension MOS in standard CMOS flow 审中-公开
    在标准CMOS流程中形成反向扩展MOS

    公开(公告)号：US20080029830A1

    公开(公告)日：2008-02-07

    申请号：US11496838

    申请日：2006-08-01

    申请人： Yung Chih Tsai ,  Chih-Ping Chao ,  Chih-Sheng Chang ,  Michael Yu

    发明人： Yung Chih Tsai ,  Chih-Ping Chao ,  Chih-Sheng Chang ,  Michael Yu

    IPC分类号： H01L29/76

    CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L29/0646 ,  H01L29/086 ,  H01L29/78 ,  H01L29/7835

    摘要： A reverse-extension MOS (REMOS) device and a method for forming the same are provided. The REMOS device includes a gate dielectric over a semiconductor substrate, a gate electrode on the gate dielectric, a lightly doped drain/source (LDD) region in the semiconductor substrate and having a portion extending under the gate electrode, a deep source/drain region in the semiconductor substrate, and an embedded region enclosed by a top surface of the semiconductor substrate, the LDD region, and the deep source/drain region. The embedded region is of a first conductivity type, and the LDD region and the deep source/drain region are of a second conductivity type opposite the first conductivity type. The embedded region and the LDD region are preferably formed simultaneously with the formation of a LDD region and a pocket region of an additional MOS device, respectively.

    摘要翻译： 提供了反向延伸MOS（REMOS）器件及其形成方法。 REMOS器件包括在半导体衬底上的栅极电介质，栅极电介质上的栅极电极，半导体衬底中的轻掺杂漏极/源极（LDD）区域，并且具有在栅电极下延伸的部分，深源极/漏极区域 在半导体衬底中，以及由半导体衬底的顶表面，LDD区和深源极/漏极区包围的嵌入区域。 嵌入区域是第一导电类型，并且LDD区域和深源极/漏极区域是与第一导电类型相反的第二导电类型。 优选地，嵌入区域和LDD区域同时形成附加MOS器件的LDD区域和口袋区域。