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41.发明授权Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 4/15 and 64-symbol mapping, and bit interleaving method using same 有权具有长度为64800和码率为4/15和64符号映射的低密度奇偶校验码字的位交织器，以及使用相同的比特交织方法公开(公告)号：US09577680B2
公开(公告)日：2017-02-21
申请号：US14626140
申请日：2015-02-19
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H03M13/2792 , H03M13/1102 , H03M13/1128 , H03M13/116 , H03M13/1185 , H03M13/255 , H03M13/2778 , H03M13/616 , H03M13/6552 , H04L1/0058 , H04L1/0071
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储长度为64800和码率为4/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于64符号映射的调制器。
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42.发明授权Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and quadrature phase shift keying, and bit interleaving method using same 有权具有长度为64800和码率为2/15的正交相移键控的低密度奇偶校验码字的比特交织器和使用相同的比特交织方法公开(公告)号：US09553609B2
公开(公告)日：2017-01-24
申请号：US14606978
申请日：2015-01-27
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H03M13/1165 , H03M13/255 , H03M13/2757 , H03M13/2778 , H03M13/2792 , H04L1/0057 , H04L1/0058 , H04L1/0071 , H04L1/0076 , H04L2001/0093
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储具有长度为64800和码率为2/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于正交相移键控（QPSK）调制的调制器。
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43.发明授权Modulator and modulation method using non-uniform 16-symbol signal constellation for low-density parity check codeword having 3/15 code rate 有权对于具有3/15码率的低密度奇偶校验码字，使用不均匀16符号信号星座的调制器和调制方法公开(公告)号：US09520898B2
公开(公告)日：2016-12-13
申请号：US14618972
申请日：2015-02-10
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H03M13/1165 , H03M13/255 , H03M13/2792 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0042 , H04L1/0057 , H04L1/0058 , H04L1/0071 , H04L27/3422
Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 3/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.
Abstract translation: 公开了一种使用非均匀16符号信号星座的调制器和调制方法。 调制器包括存储器和处理器。 存储器接收与码率为3/15的低密度奇偶校验（LDPC）码对应的码字。 处理器将码字映射为4比特的16位符号的不均匀16符号信号星座。
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44.发明授权Low density parity check encoder having length of 64800 and code rate of 5/15, and low density parity check encoding method using the same 有权长度为64800，码率为5/15的低密度奇偶校验编码器，以及使用其的低密度奇偶校验编码方法公开(公告)号：US09496896B2
公开(公告)日：2016-11-15
申请号：US14495803
申请日：2014-09-24
Inventor： Sung-Ik Park , Heung-Mook Kim , Sun-Hyoung Kwon , Nam-Ho Hur
CPC classification number: H03M13/1185 , H03M13/1102 , H03M13/1105 , H03M13/116 , H03M13/1165 , H03M13/255 , H03M13/616 , H04L1/0041 , H04L1/0043 , H04L1/0057 , H04L1/0065
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
Abstract translation: 公开了一种低密度奇偶校验（LDPC）编码器，LDPC解码器和LDPC编码方法。 LDPC编码器包括第一存储器，第二存储器和处理器。 第一存储器存储长度为64800和码率为5/15的LDPC码字。 第二存储器被初始化为0.处理器通过使用与奇偶校验矩阵（PCM）相对应的序列执行相对于第二存储器的累积来生成与信息位对应的LDPC码字。
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45.发明授权Low density parity check encoder having length of 64800 and code rate of 2/15, and low density parity check encoding method using the same 有权长度为64800，码率为2/15的低密度奇偶校验编码器，以及使用该码的低密度奇偶校验编码方法公开(公告)号：US09490843B2
公开(公告)日：2016-11-08
申请号：US14496457
申请日：2014-09-25
Inventor： Sung-Ik Park , Heung-Mook Kim , Sun-Hyoung Kwon , Nam-Ho Hur
CPC classification number: H03M13/1177 , H03M13/1102 , H03M13/1105 , H03M13/116 , H03M13/1165 , H03M13/1185 , H03M13/255 , H03M13/616 , H03M13/6552 , H04L1/0057
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
Abstract translation: 公开了一种低密度奇偶校验（LDPC）编码器，LDPC解码器和LDPC编码方法。 LDPC编码器包括第一存储器，第二存储器和处理器。 第一存储器存储长度为64800，码率为2/15的LDPC码字。 第二存储器被初始化为0.处理器通过使用与奇偶校验矩阵（PCM）相对应的序列执行相对于第二存储器的累积来生成与信息位对应的LDPC码字。
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Patent Agency Ranking
46.发明授权公开(公告)号：US12095554B2
公开(公告)日：2024-09-17
申请号：US18165876
申请日：2023-02-07
Inventor： Sung-Ik Park , Jae-Young Lee , Sun-Hyoung Kwon , Nam-Ho Hur , Heung-Mook Kim
CPC classification number: H04L1/0041 , H04J99/00 , H04L1/0057 , H04L1/0071 , H04L5/0014 , H04L5/0075 , H04L27/2626
Abstract: An apparatus and method for transmitting broadcast signal to which channel bonding is applied are disclosed. The apparatus according to the present invention includes an input formatting unit configured to generate baseband packets corresponding to a plurality of packet types using data corresponding to a physical layer pipe; a stream partitioner configured to partition the baseband packets into a plurality of partitioned streams corresponding to the plurality of packet types; BICM units configured to perform error correction encoding, interleaving and modulation corresponding to the plurality of partitioned streams, respectively; and waveform generators configured to generate RF transmission signals corresponding to the plurality of partitioned streams, respectively.
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47.发明授权公开(公告)号：US11757689B2
公开(公告)日：2023-09-12
申请号：US17746799
申请日：2022-05-17
Inventor： Jae-Young Lee , Sung-Ik Park , Sun-Hyoung Kwon , Heung-Mook Kim , Nam-Ho Hur
IPC: H04J3/00 , H04L27/26 , H04J11/00 , H04L1/00 , H04L27/34 , H04W52/34 , H04L65/611 , H04L5/22 , H04W52/04 , H04W72/0446
CPC classification number: H04L27/2613 , H04J11/004 , H04L1/0063 , H04L1/0071 , H04L5/22 , H04L27/26 , H04L27/2602 , H04L27/34 , H04L65/611 , H04W52/04 , H04W52/346 , H04W72/0446 , H04L27/26025 , H04L27/26136 , Y02D30/70
Abstract: An apparatus and method for generating broadcast signal frame using layered division multiplexing are disclosed. The apparatus includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time-interleaved signal.
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公开(公告)号：US11722155B2
公开(公告)日：2023-08-08
申请号：US17165614
申请日：2021-02-02
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Bo-Mi Lim , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H03M13/2792 , G06F11/1076 , H03M13/1102 , H03M13/116 , H03M13/1148 , H03M13/1185 , H03M13/255 , H03M13/2778 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0045 , H04L1/0058 , H04L1/0071
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
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公开(公告)号：US11700015B2
公开(公告)日：2023-07-11
申请号：US17500848
申请日：2021-10-13
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Bo-Mi Lim , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H03M13/1102 , G06F11/1076 , H03M13/116 , H03M13/1185 , H03M13/255 , H03M13/2778
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
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公开(公告)号：US11646824B2
公开(公告)日：2023-05-09
申请号：US17882843
申请日：2022-08-08
Inventor： Jae-Young Lee , Sung-Ik Park , Sun-Hyoung Kwon , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H04L1/0643 , H04B7/022 , H04L1/0681 , H04L25/49 , H04L27/367
Abstract: Disclosed herein are a gateway-signaling method for Multiple-Input Single-Output (MISO) operation and an apparatus for the same. An apparatus for transmitting a broadcast signal according to an embodiment of the present invention includes a predistortion unit for performing predistortion for decorrelating signals corresponding to transmitters using the number of transmitters used for MISO and a transmitter coefficient index that are identified using a timing and management packet transmitted through a Studio-to-Transmitter Link (STL), thereby generating a pre-distorted signal; and an RF signal generation unit for generating an RF transmission signal using the pre-distorted signal corresponding to the transmitter coefficient index.
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