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公开(公告)号：US07911470B1
公开(公告)日：2011-03-22
申请号：US11955335
申请日：2007-12-12
IPC分类号： G06T1/20
CPC分类号： G09G5/001 , G09G5/363 , G09G5/393 , G09G2352/00 , G09G2360/125
摘要： An apparatus and method for fairly arbitrating between clients with varying workloads. The clients are configured in a pipeline for processing graphics data. An arbitration unit selects requests from each of the clients to access a shared resource. Each client provides a signal to the arbitration unit for each clock cycle. The signal indicates whether the client is waiting for a response from the arbitration unit and whether the client is not blocked from outputting processed data to a downstream client. The signals from each client are integrated over several clock cycles to determine a servicing priority for each client. Arbitrating based on the servicing priorities improves performance of the pipeline by ensuring that each client is allocated access to the shared resource based on the aggregate processing load distribution.
摘要翻译： 一种用于在具有不同工作负载的客户端之间进行公平仲裁的装置和方法。 客户端被配置在流水线中以处理图形数据。 仲裁单元选择来自每个客户端的访问共享资源的请求。 每个客户端在每个时钟周期向仲裁单元提供一个信号。 该信号指示客户端是否正在等待来自仲裁单元的响应以及客户端是否被阻止不将处理的数据输出到下游客户端。 来自每个客户端的信号在几个时钟周期内被集成，以确定每个客户端的服务优先级。 基于服务优先级的仲裁通过确保每个客户端基于总体处理负载分配分配对共享资源的访问来提高流水线的性能。
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42.发明授权Logical design of graphics system with reduced shadowed state memory requirements 有权具有减少阴影状态存储器要求的图形系统的逻辑设计公开(公告)号：US07898546B1
公开(公告)日：2011-03-01
申请号：US11556646
申请日：2006-11-03
IPC分类号： G06T1/60
CPC分类号： G06T1/60
摘要： A graphics processing unit is designed to have validation logic utilizing a reduced memory space shadow memory as a source of state information for performing validation of commands. A semantic analysis is performed to generate the validation logic such that the reduced memory space shadow memory has a size small than a memory size required to store a full representation of a set of state variables associated with a class of commands.
摘要翻译： 图形处理单元被设计为具有利用减小的存储空间影子存储器作为用于执行命令验证的状态信息的源的验证逻辑。 执行语义分析以生成验证逻辑，使得减少的存储器空间影子存储器的尺寸小于存储与一组命令相关联的一组状态变量的完整表示所需的存储器大小。
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43.发明授权Apparatus, system, and method for reducing shadowed state memory requirements for identifying driver command exceptions in a graphics system 有权用于减少用于识别图形系统中的驱动程序命令异常的阴影状态存储器要求的装置，系统和方法公开(公告)号：US07768515B1
公开(公告)日：2010-08-03
申请号：US11556635
申请日：2006-11-03
IPC分类号： G06T1/00
CPC分类号： G06T1/20
摘要： A graphics processing unit has a reduced memory space shadow memory as a source of state information for performing validation of commands. The reduced memory space shadow memory is smaller in size than a full version of state variables associated with an abstract state machine representation of a class of commands received from a software driver. The reduced memory space shadow memory is used by validation logic to detect exceptions indicative of an illegal command or sequence of commands.
摘要翻译： 图形处理单元具有减小的存储空间影子存储器作为用于执行命令验证的状态信息源。 缩小的内存空间影子内存的大小要比与从软件驱动程序接收的一组命令的抽象状态机表示相关联的状态变量的完整版本小。 减少的存储空间影子存储器被验证逻辑用来检测指示非法命令或命令序列的异常。
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44.发明授权公开(公告)号：US07739556B1
公开(公告)日：2010-06-15
申请号：US11934686
申请日：2007-11-02
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0715 , G06F11/0751
摘要： A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.
摘要翻译： 使用应用编程接口（API）将编程到处理器中的状态信息进行覆盖的方法和系统避免了在处理器中引入错误状况。 处理器内的覆盖监视单元存储被覆盖的任何设置的编程状态，以便当错误条件不再存在时可以恢复编程状态。 覆盖监视器单元通过强制设置为不引起错误条件的合法值来覆盖编程状态。 处理器能够在不通知设备驱动程序的情况下继续运行，因为避免了错误条件，所以发生了错误状况。
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公开(公告)号：US07564456B1
公开(公告)日：2009-07-21
申请号：US11332695
申请日：2006-01-13
CPC分类号： G06T15/005 , G06T11/40 , G09G2360/122
摘要： A graphics pipeline rasterizes primitives and generates a stream of groups of pixels, such as a stream of pixel quads. A tile coalesce unit received the stream of groups of pixels and generates pixel tiles for use by downstream pixel processing units. The pixel tiles facilitate hazard checks and transaction coherency.
摘要翻译： 图形流水线对原始图形进行栅格化，并生成一组像素流，如像素四边形流。 瓦片聚结单元接收到像素组的流，并生成用于下游像素处理单元的像素瓦片。 像素瓦片有助于危害检查和事务一致性。
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公开(公告)号：US07292242B1
公开(公告)日：2007-11-06
申请号：US10917093
申请日：2004-08-11
申请人： Craig M. Wittenbrink , Henry Packard Moreton , Douglas A. Voorhies , John S. Montrym , Vimal S. Parikh
发明人： Craig M. Wittenbrink , Henry Packard Moreton , Douglas A. Voorhies , John S. Montrym , Vimal S. Parikh
IPC分类号： G06T15/40
CPC分类号： G06T15/30
摘要： Clipping techniques introduce additional vertices into existing primitives without requiring creation of new primitives. For an input triangle with one vertex on the invisible side of a clipping surface, a quadrangle can be defined. The vertices of the quadrangle are the two internal vertices of the input triangle and two clipped vertices. For determining attribute values for pixel shading, three vertices of the quadrangle are selected, and a parameter value for an attribute equation is computed using the three selected vertices. For determining pixel coverage for the quadrangle, the three edges that do not correspond to the edge created by clipping are used.
摘要翻译： 剪切技术将额外的顶点引入现有的基元，而不需要创建新的基元。 对于在剪切表面的不可见侧有一个顶点的输入三角形，可以定义四边形。 四边形的顶点是输入三角形的两个内部顶点和两个剪切顶点。 为了确定像素阴影的属性值，选择四边形的三个顶点，并且使用三个选定的顶点来计算属性方程的参数值。 为了确定四边形的像素覆盖率，使用与削波产生的边缘不对应的三个边。
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公开(公告)号：US07286134B1
公开(公告)日：2007-10-23
申请号：US10740229
申请日：2003-12-17
CPC分类号： G06T15/005 , G06T1/60 , H04N19/423
摘要： A tiled graphics memory permits z data and stencil data to be stored in different portions of a tile. The tile may be further divided into data sections, each of which may have a byte size corresponding to a memory access size.
摘要翻译： 平铺的图形存储器允许z数据和模板数据存储在瓦片的不同部分中。 瓦片可以进一步划分为数据部分，每个部分可以具有对应于存储器访问大小的字节大小。
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公开(公告)号：US07068278B1
公开(公告)日：2006-06-27
申请号：US10732944
申请日：2003-12-11
CPC分类号： G06F3/1446 , G09G5/39 , H04N9/3147
摘要： A graphics processing unit, which includes a clock generator configured to generate a clock signal and a controller coupled to the clock generator. The controller is configured to receive the clock signal, compare the clock signal with a synchronization signal to generate a timing signal, and transmit the timing signal to a second graphics processing unit connected to the graphics processing unit.
摘要翻译： 图形处理单元，其包括被配置为产生时钟信号的时钟发生器和耦合到时钟发生器的控制器。 控制器被配置为接收时钟信号，将时钟信号与同步信号进行比较以产生定时信号，并将定时信号发送到连接到图形处理单元的第二图形处理单元。
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公开(公告)号：US06853382B1
公开(公告)日：2005-02-08
申请号：US09687453
申请日：2000-10-13
CPC分类号： G06F13/161 , G06T1/60 , G09G5/001 , G09G5/39 , G09G2360/12 , G09G2360/123
摘要： A memory system having a number of partitions each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to the memory client of a single partition memory subsystem. The memory request specifies a location in the memory system and a transfer size. A partition receives input from an arbiter circuit which, in turn, receives input from a number of client queues for the partition. The arbiter circuit selects a client queue based on a priority policy such as round robin or least recently used or a static or dynamic policy. A router receives a memory request, determines the one or more partitions needed to service the request and stores the request in the client queues for the servicing partitions. In one embodiment, an additional arbiter circuit selects memory requests from one of a subset of the memory clients and forwards the requests to a routing circuit, thereby providing a way for the subset of memory clients to share the client queues and routing circuit. Alternatively, a memory client can make requests directed to a particular partition in which case no routing circuit is required. For a read request that requires more than one partition to service, the memory system must collect the read data from read queues for the various partitions and deliver the collected data back to the proper client. Read queues can provide data in non-fifo order to satisfy an memory client that can receive data out-of-order.
摘要翻译： 一种具有多个分区的存储器系统，每个分区各自操作以独立地维护来自多个存储器客户端的存储器请求，同时保持对单个分区存储器子系统的存储器客户端的外观。 存储器请求指定存储器系统中的位置和传送大小。 分区接收来自仲裁器电路的输入，仲裁器电路又接收来自分区的多个客户端队列的输入。 仲裁器电路基于诸如轮询或最近使用的优先策略或静态或动态策略来选择客户端队列。 路由器接收存储器请求，确定服务请求所需的一个或多个分区，并将请求存储在服务分区的客户机队列中。 在一个实施例中，另外的仲裁器电路从存储器客户端的子集中的一个选择存储器请求，并将请求转发到路由电路，从而为存储器客户端的子集共享客户机队列和路由电路提供一种方式。 或者，存储器客户端可以将请求定向到特定分区，在这种情况下不需要路由电路。 对于需要多个分区进行服务的读取请求，内存系统必须从各个分区的读取队列中收集读取的数据，并将收集的数据传送回正确的客户端。 读队列可以以非fifo命令提供数据，以满足可以接收无序数据的内存客户端。
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公开(公告)号：US06779170B1
公开(公告)日：2004-08-17
申请号：US10316678
申请日：2002-12-11
申请人： John S. Montrym
发明人： John S. Montrym
IPC分类号： G06F1750
CPC分类号： G06F17/5027
摘要： Method and apparatus for providing logic emulation. Specifically, the present invention provides logic emulation by using waferscale integration.
摘要翻译： 提供逻辑仿真的方法和装置。 具体地，本发明通过使用晶片级整合来提供逻辑仿真。
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