Hardware override of application programming interface programmed state
    1.
    发明授权
    Hardware override of application programming interface programmed state 有权
    硬件覆盖应用程序编程接口编程状态

    公开(公告)号:US07739556B1

    公开(公告)日:2010-06-15

    申请号:US11934686

    申请日:2007-11-02

    IPC分类号: G06F11/00

    摘要: A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.

    摘要翻译: 使用应用编程接口(API)将编程到处理器中的状态信息进行覆盖的方法和系统避免了在处理器中引入错误状况。 处理器内的覆盖监视单元存储被覆盖的任何设置的编程状态,以便当错误条件不再存在时可以恢复编程状态。 覆盖监视器单元通过强制设置为不引起错误条件的合法值来覆盖编程状态。 处理器能够在不通知设备驱动程序的情况下继续运行,因为避免了错误条件,所以发生了错误状况。

    Hardware override of application programming interface programmed state
    2.
    发明授权
    Hardware override of application programming interface programmed state 有权
    硬件覆盖应用程序编程接口编程状态

    公开(公告)号:US08493395B2

    公开(公告)日:2013-07-23

    申请号:US13550468

    申请日:2012-07-16

    摘要: A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.

    摘要翻译: 使用应用编程接口(API)将编程到处理器中的状态信息进行覆盖的方法和系统避免了在处理器中引入错误状况。 处理器内的覆盖监视单元存储被覆盖的任何设置的编程状态,以便当错误条件不再存在时可以恢复编程状态。 覆盖监视器单元通过强制设置为不引起错误条件的合法值来覆盖编程状态。 处理器能够在不通知设备驱动程序的情况下继续运行,因为避免了错误条件,所以发生了错误状况。

    Hardware override of application programming interface programmed state
    3.
    发明授权
    Hardware override of application programming interface programmed state 有权
    硬件覆盖应用程序编程接口编程状态

    公开(公告)号:US08228338B1

    公开(公告)日:2012-07-24

    申请号:US11625136

    申请日:2007-01-19

    IPC分类号: G06F13/14 G06F11/00 G06T1/00

    摘要: A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.

    摘要翻译: 使用应用编程接口(API)将编程到处理器中的状态信息进行覆盖的方法和系统避免了在处理器中引入错误状况。 处理器内的覆盖监视单元存储被覆盖的任何设置的编程状态,以便当错误条件不再存在时可以恢复编程状态。 覆盖监视器单元通过强制设置为不引起错误条件的合法值来覆盖编程状态。 处理器能够在不通知设备驱动程序的情况下继续运行,因为避免了错误条件,所以发生了错误状况。

    HARDWARE OVERRIDE OF APPLICATION PROGRAMMING INTERFACE PROGRAMMED STATE
    5.
    发明申请
    HARDWARE OVERRIDE OF APPLICATION PROGRAMMING INTERFACE PROGRAMMED STATE 有权
    应用编程接口编程状态的硬件

    公开(公告)号:US20120284568A1

    公开(公告)日:2012-11-08

    申请号:US13550468

    申请日:2012-07-16

    IPC分类号: G06F11/30

    摘要: A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.

    摘要翻译: 使用应用编程接口(API)将编程到处理器中的状态信息进行覆盖的方法和系统避免了在处理器中引入错误状况。 处理器内的覆盖监视单元存储被覆盖的任何设置的编程状态,以便当错误条件不再存在时可以恢复编程状态。 覆盖监视器单元通过强制设置为不引起错误条件的合法值来覆盖编程状态。 处理器能够在不通知设备驱动程序的情况下继续运行,因为避免了错误条件,所以发生了错误状况。

    System, method and article of manufacture for a programmable processing model with instruction set
    8.
    发明授权
    System, method and article of manufacture for a programmable processing model with instruction set 有权
    具有指令集的可编程处理模型的系统,方法和制造

    公开(公告)号:US08259122B1

    公开(公告)日:2012-09-04

    申请号:US11942577

    申请日:2007-11-19

    IPC分类号: G09G5/00 G06T1/00

    CPC分类号: G06T15/005 G06T15/503

    摘要: A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.

    摘要翻译: 提供了一种用于计算机图形管线中的可编程处理的系统,方法和制造物品。 最初,从源缓冲区接收数据。 此后,对数据执行可编程操作以产生输出。 操作是可编程的,因为用户可以利用来自预定指令集的指令来产生它们。 这样的输出被存储在寄存器中。 在运行期间,存储在寄存器中的输出用于对数据执行可编程操作。

    Alignment and ordering of vector elements for single instruction multiple data processing
    9.
    发明授权
    Alignment and ordering of vector elements for single instruction multiple data processing 有权
    用于单指令多数据处理的向量元素的对齐和排序

    公开(公告)号:US07793077B2

    公开(公告)日:2010-09-07

    申请号:US11702659

    申请日:2007-02-06

    IPC分类号: G06F9/34

    摘要: The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register. Then, a subset of elements are selected from the first register and the second register. The elements from the subset are then replicated into the elements in the third register in a particular order suitable for subsequent SIMD vector processing.

    摘要翻译: 本发明提供用于SIMD处理的向量元素的对准和排序。 在用于SIMD处理的向量元素的对齐中,一个向量从存储器单元加载到第一寄存器中,另一个向量从存储器单元加载到第二寄存器中。 第一个向量包含要生成的对齐向量的第一个字节。 然后,确定指定对齐向量的第一个字节的起始字节。 接下来,从第一寄存器提取向量,并且从第一寄存器的第一字节的第一位开始的第二寄存器继续通过第二寄存器中的位。 最后,将所提取的矢量复制到第三寄存器中,使得第三寄存器包含对准用于SIMD处理的多个元素。 在用于SIMD处理的向量元素的排序中,将第一向量从存储器单元加载到第一寄存器中,并且将第二向量从存储器单元加载到第二寄存器中。 然后,从第一寄存器和第二寄存器中选择元件的子集。 然后将来自子集的元素以适合于随后的SIMD向量处理的特定顺序复制到第三寄存器中的元素中。

    Mapping memory partitions to virtual memory pages
    10.
    发明授权
    Mapping memory partitions to virtual memory pages 有权
    将内存分区映射到虚拟内存页面

    公开(公告)号:US07620793B1

    公开(公告)日:2009-11-17

    申请号:US11467679

    申请日:2006-08-28

    摘要: Systems and methods for addressing memory using non-power-of-two virtual memory page sizes improve graphics memory bandwidth by distributing graphics data for efficient access during rendering. Various partition strides may be selected for each virtual memory page to modify the number of sequential addresses mapped to each physical memory partition and change the interleaving granularity. The addressing scheme allows for modification of a bank interleave pattern for each virtual memory page to reduce bank conflicts and improve memory bandwidth utilization. The addressing scheme also allows for modification of a partition interleave pattern for each virtual memory page to distribute accesses amongst multiple partitions and improve memory bandwidth utilization.

    摘要翻译: 使用非二功能虚拟内存页大小寻址内存的系统和方法通过在渲染过程中分配图形数据进行高效访问来提高图形内存带宽。 可以为每个虚拟存储器页面选择各种分段步长,以修改映射到每个物理存储器分区的顺序地址的数量并改变交织粒度。 寻址方案允许修改每个虚拟存储器页面的存储体交织模式以减少存储体冲突并提高存储器带宽利用率。 寻址方案还允许修改每个虚拟存储器页面的分区交织模式以分布多个分区之间的访问并提高存储器带宽利用率。