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    Method and system for efficient antialiased rendering
    1.
    发明授权
    Method and system for efficient antialiased rendering 有权
    用于高效抗锯齿渲染的方法和系统

    公开(公告)号：US08692844B1

    公开(公告)日：2014-04-08

    申请号：US09675099

    申请日：2000-09-28

    申请人： Steven E. Molnar ,  David B. Kirk ,  John Stephen Montrym ,  Douglas A. Voorhies

    发明人： Steven E. Molnar ,  David B. Kirk ,  John Stephen Montrym ,  Douglas A. Voorhies

    IPC分类号： G09G5/00 ,  G06T11/20 ,  G06T11/40 ,  G09G5/14

    CPC分类号： G06T11/203 ,  G06T11/40 ,  G09G5/14

    摘要： A method and system are disclosed for antialiased rendering a plurality of pixels in a computer system. The method and system comprise providing a fixed storage area and providing a plurality of sequential format levels for the plurality of pixels within the fixed storage area. The plurality of format levels represent pixels with varying degrees of complexity in subpixel geometry visible within the pixel. A system and method in accordance with the present invention provides at least the following format levels: one-fragment format, used when one surface fully covers a pixel; two-fragment format, used when two surfaces together cover a pixel; and multisample format, used when three or more surfaces cover a pixel. The method and system further comprise storing the plurality of pixels at a lowest appropriate format level within the fixed storage area, so that a minimum amount of data is transferred to and from the fixed storage area. The method and system further comprise procedures for converting pixels from one format level to take into account newly rendered pixel fragments. All formats represent depth values in a consistent manner so that fragments rendered during later rendering passes match depth values resulting from rendering the same primitive in earlier passes. Thus, the invention enables high-quality antialiasing with minimal data transferred to and from the fixed storage area, while supporting multi-pass rendering.

    摘要翻译： 公开了一种用于在计算机系统中抗锯齿渲染多个像素的方法和系统。 所述方法和系统包括提供固定存储区域并为固定存储区域内的多个像素提供多个顺序格式级别。 多个格式级别表示在像素内可见的子像素几何形状具有不同程度的复杂度的像素。 根据本发明的系统和方法至少提供以下格式级别：当一个表面完全覆盖像素时使用的单片段格式; 两片段格式，当两个表面一起覆盖一个像素时使用; 和多重采样格式，当三个或更多个表面覆盖像素时使用。 所述方法和系统还包括将所述多个像素存储在所述固定存储区域内的最低适当格式级别，使得最小量的数据被传送到所述固定存储区域和从所述固定存储区域传送。 该方法和系统还包括用于从一个格式级别转换像素以考虑新渲染的像素片段的过程。 所有格式都以一致的方式表示深度值，以便在后续渲染过程中渲染的片段匹配在较早的通过中渲染相同原语而产生的深度值。 因此，本发明能够以最小的数据传输到固定存储区域和从固定存储区域传输高质量的抗锯齿，同时支持多遍渲染。

    Small primitive detection to optimize compression and decompression in a graphics processor
    2.
    发明授权
    Small primitive detection to optimize compression and decompression in a graphics processor 有权
    小图形检测优化图形处理器中的压缩和解压缩

    公开(公告)号：US08508544B1

    公开(公告)日：2013-08-13

    申请号：US11593368

    申请日：2006-11-02

    申请人： Steven E. Molnar ,  Franklin C. Crow

    发明人： Steven E. Molnar ,  Franklin C. Crow

    IPC分类号： G06T9/00

    CPC分类号： G06T9/00

    摘要： A method and system for selective enablement of tile compression. The method includes receiving a graphics primitive for processing in a set-up unit of a graphics processor and determining a primitive characteristic that indicates a probability of whether a final compression of a tile related to the primitive will be retained. Compression for the tile related to the primitive is allowed when the characteristic indicates the final compression will be retained. Compression for the tile related to the primitive is disallowed in the characteristic indicates the final compression will not be retained.

    摘要翻译： 一种用于选择性地实现瓦片压缩的方法和系统。 该方法包括接收用于在图形处理器的设置单元中进行处理的图形基元，并且确定指示是否将保留与该图元相关的瓦片的最终压缩的概率的原始特性。 当特征指示最终压缩将被保留时，允许与原语相关的瓦片的压缩。 对于与原语相关的瓦片的压缩不允许在特征中表示最终的压缩将不会被保留。

    Coalescing to avoid read-modify-write during compressed data operations
    3.
    发明授权
    Coalescing to avoid read-modify-write during compressed data operations 有权
    聚合以避免压缩数据操作期间的读 - 修改 - 写

    公开(公告)号：US08427495B1

    公开(公告)日：2013-04-23

    申请号：US11954722

    申请日：2007-12-12

    申请人： John H. Edmondson ,  Robert A. Alfieri ,  Michael F. Harris ,  Steven E. Molnar

    发明人： John H. Edmondson ,  Robert A. Alfieri ,  Michael F. Harris ,  Steven E. Molnar

    IPC分类号： G06F12/02

    CPC分类号： G06T1/60 ,  H04N19/423

    摘要： Write operations to a unit of compressible memory, known as a compression tile, are examined to see if data blocks to be written completely cover a single compression tile. If the data blocks completely cover a single compression tile, the write operations are coalesced into a single write operation and the single compression tile is overwritten with the data blocks. Coalescing multiple write operations into a single write operation improves performance, because it avoids the read-modify-write operations that would otherwise be needed.

    摘要翻译： 对可压缩存储器（称为压缩片）的单位进行写操作，以查看要写入的数据块是否完全覆盖单个压缩片。 如果数据块完全覆盖单个压缩块，则写入操作合并为单个写入操作，并且单个压缩块被数据块覆盖。 将多个写入操作合并为单个写入操作会提高性能，因为它避免了否则需要的读取 - 修改 - 写入操作。

    Late Z testing for multiple render targets
    4.
    发明授权
    Late Z testing for multiple render targets 有权
    Late Z测试用于多个渲染目标

    公开(公告)号：US08243069B1

    公开(公告)日：2012-08-14

    申请号：US11934051

    申请日：2007-11-01

    申请人： Mark J. French ,  Phillip Keslin ,  Steven E Molnar ,  Adam Clark Weitkemper

    发明人： Mark J. French ,  Phillip Keslin ,  Steven E Molnar ,  Adam Clark Weitkemper

    IPC分类号： G06T15/40 ,  G09G5/36 ,  G09G5/37

    CPC分类号： G06T15/40

    摘要： The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.

    摘要翻译： 当本发明涉及当将存储器组织在可能不匹配着色器数量的多个分区中时，用于计算每个样本后z测试覆盖的新系统和方法。 着色器输出的阴影像素可以由几个z光栅操作单元之一处理。 可以独立于存储器分区的数量和z个光栅操作单元的数量来配置着色处理能力。 本发明还涉及使用具有单个或多个存储器分区的具有多个渲染目标的不同z测试模式的新系统和方法。 渲染性能可以通过使用早期z测试模式来改善，用于在阴影之前消除不可见样本。

    Method and system for improving data coherency in a parallel rendering system
    5.
    发明授权
    Method and system for improving data coherency in a parallel rendering system 有权
    用于提高并行渲染系统中数据一致性的方法和系统

    公开(公告)号：US08139069B1

    公开(公告)日：2012-03-20

    申请号：US11556660

    申请日：2006-11-03

    申请人： Steven E. Molnar ,  Cass W. Everitt ,  Roger L. Allen ,  Gary M. Tarolli ,  John M. Danskin

    发明人： Steven E. Molnar ,  Cass W. Everitt ,  Roger L. Allen ,  Gary M. Tarolli ,  John M. Danskin

    IPC分类号： G06F15/80

    CPC分类号： G06T15/005 ,  G06F9/522 ,  G06T2210/52

    摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system that includes the steps of maintaining a time stamp for a group of tiles of work that are associated with each of the plurality of the texture streams and are associated with a specified area in screen space, and utilizing the time stamps to counter divergences in the independent processing of the plurality of texture streams.

    摘要翻译： 公开了一种用于提高并行渲染系统中数据一致性的方法和系统。 具体地，本发明的一个实施例阐述了一种用于在并行渲染系统中管理多个独立处理的纹理流的方法，该方法包括以下步骤：维护与多个相关联的工作的一组瓦片的时间戳 的纹理流并且与屏幕空间中的指定区域相关联，并且利用时间戳来反复在多个纹理流的独立处理中的分歧。

    PARALLEL ARRAY ARCHITECTURE FOR A GRAPHICS PROCESSOR
    6.
    发明申请
    PARALLEL ARRAY ARCHITECTURE FOR A GRAPHICS PROCESSOR 有权
    图形处理器的并行阵列架构

    公开(公告)号：US20120026171A1

    公开(公告)日：2012-02-02

    申请号：US13269462

    申请日：2011-10-07

    申请人： John M. Danskin ,  John S. Montrym ,  John Erik Lindholm ,  Steven E. Molnar ,  Mark French

    发明人： John M. Danskin ,  John S. Montrym ,  John Erik Lindholm ,  Steven E. Molnar ,  Mark French

    IPC分类号： G06T15/50

    CPC分类号： G06T15/005 ,  G06T2210/52 ,  G09G5/363 ,  G09G5/393 ,  G09G2360/06 ,  G09G2360/122

    摘要： A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. A crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.

    摘要翻译： 用于图形处理器的并行阵列架构包括包括多个处理簇的多线程核心阵列，每个处理簇包括至少一个可操作以执行从覆盖数据生成像素数据的像素着色器程序的处理核心; 光栅化器，被配置为生成多个像素中的每一个的覆盖数据; 以及像素分布逻辑，被配置为将覆盖数据从光栅化器传送到多线程核心阵列中的处理集群之一。 耦合到每个处理集群的交叉开关被配置为将像素数据从处理集群传送到具有多个分区的帧缓冲器。

    ALPHA-TO-COVERAGE USING VIRTUAL SAMPLES
    7.
    发明申请
    ALPHA-TO-COVERAGE USING VIRTUAL SAMPLES 有权
    使用虚拟样品的ALPHA-TO-COVERAGE

    公开(公告)号：US20110090250A1

    公开(公告)日：2011-04-21

    申请号：US12904927

    申请日：2010-10-14

    申请人： Steven E. MOLNAR ,  Emmett M. KILGARIFF ,  Walter E. DONOVAN ,  Christian AMSINCK ,  Robert OHANNESSIAN

    发明人： Steven E. MOLNAR ,  Emmett M. KILGARIFF ,  Walter E. DONOVAN ,  Christian AMSINCK ,  Robert OHANNESSIAN

    IPC分类号： G09G5/00

    CPC分类号： G06T15/503 ,  G06T15/005 ,  G09G5/363 ,  G09G5/393 ,  G09G2360/123

    摘要： One embodiment of the present invention sets forth a technique for converting alpha values into pixel coverage masks. Geometric coverage is sampled at a number of “real” sample positions within each pixel. Color and depth values are computed for each of these real samples. Fragment alpha values are used to determine an alpha coverage mask for the real samples and additional “virtual” samples, in which the number of bits set in the mask bits is proportional to the alpha value. An alpha-to-coverage mode uses the virtual samples to increase the number of transparency levels for each pixel compared with using only real samples. The alpha-to-coverage mode may be used in conjunction with virtual coverage anti-aliasing to provide higher-quality transparency for rendering anti-aliased images.

    摘要翻译： 本发明的一个实施例提出了一种将α值转换为像素覆盖掩码的技术。 在每个像素内的多个“实”样本位置采样几何覆盖。 为这些实际样本中的每一个计算颜色和深度值。 片段α值用于确定实际样本和附加“虚拟”样本的alpha覆盖掩码，其中掩码位中设置的位数与alpha值成比例。 与仅使用真实样本相比，alpha到覆盖模式使用虚拟样本来增加每个像素的透明度级别数。 alpha到覆盖模式可以与虚拟覆盖抗锯齿一起使用，以提供用于渲染抗锯齿图像的更高质量的透明度。

    EFFICIENT LINE AND PAGE ORGANIZATION FOR COMPRESSION STATUS BIT CACHING
    9.
    发明申请
    EFFICIENT LINE AND PAGE ORGANIZATION FOR COMPRESSION STATUS BIT CACHING 有权
    用于压缩状态位高速缓存的有效线和组合

    公开(公告)号：US20110087840A1

    公开(公告)日：2011-04-14

    申请号：US12901452

    申请日：2010-10-08

    申请人： David B. GLASCO ,  Peter B. HOLMQVIST ,  George R. LYNCH ,  Patrick R. MARCHAND ,  Karan MEHRA ,  James ROBERTS ,  Cass W. EVERITT ,  Steven E. MOLNAR

    发明人： David B. GLASCO ,  Peter B. HOLMQVIST ,  George R. LYNCH ,  Patrick R. MARCHAND ,  Karan MEHRA ,  James ROBERTS ,  Cass W. EVERITT ,  Steven E. MOLNAR

    IPC分类号： G06F12/00

    CPC分类号： G06F12/08 ,  G06F12/0875 ,  G06F12/1009 ,  G06F2212/401

    摘要： One embodiment of the present invention sets forth a technique for performing a memory access request to compressed data within a virtually mapped memory system comprising an arbitrary number of partitions. A virtual address is mapped to a linear physical address, specified by a page table entry (PTE). The PTE is configured to store compression attributes, which are used to locate compression status for a corresponding physical memory page within a compression status bit cache. The compression status bit cache operates in conjunction with a compression status bit backing store. If compression status is available from the compression status bit cache, then the memory access request proceeds using the compression status. If the compression status bit cache misses, then the miss triggers a fill operation from the backing store. After the fill completes, memory access proceeds using the newly filled compression status information.

    摘要翻译： 本发明的一个实施例提出了一种对包括任意数量的分区的虚拟映射的存储器系统中的压缩数据执行存储器访问请求的技术。 虚拟地址被映射到由页表项（PTE）指定的线性物理地址。 PTE被配置为存储压缩属性，其被用于定位压缩状态位缓存内的相应物理存储器页的压缩状态。 压缩状态位缓存与压缩状态位后备存储一起操作。 如果从压缩状态位缓存获得压缩状态，则存储器访问请求使用压缩状态进行。 如果压缩状态位缓存未命中，则错误触发后备存储器的填充操作。 填充完成后，使用新填充的压缩状态信息进行内存访问。