公开(公告)号：US5878029A

公开(公告)日：1999-03-02

申请号：US799412

申请日：1997-02-12

申请人： Haruhisa Hasegawa ,  Naoaki Yamanaka ,  Kouhei Shiomoto

发明人： Haruhisa Hasegawa ,  Naoaki Yamanaka ,  Kouhei Shiomoto

IPC分类号： H04L12/54 ,  H04L12/70 ,  H04Q11/04 ,  H04L12/56

CPC分类号： H04L12/5602 ,  H04Q11/0478 ,  H04L2012/5619 ,  H04L2012/5634 ,  H04L2012/5635 ,  H04L2012/5636

摘要： When bandwidth in an ATM network is controlled so as to increase in accordance with a user request, there is a considerable delay from the occurrence of the request until the bandwidth is actually changed; and there is therefore a need to control the traffic flowing in ATM network transmission paths faster and more flexibly. There is also a need to decrease the probability of overbooking occurring when deciding whether or not to accept a bandwidth change request. Route information that includes information relating to residual bandwidth is therefore collected in advance by subscriber switches that serve terminals. In response to a request from a user, a subscriber switch alone replies rapidly. During this process, the fact that there are a plurality of bandwidth change requests within the same residual bandwidth measurement period, is considered and a portion of the measured residual bandwidth is held for other bandwidth change requests. This enables the delay to be shortened. In addition, it is sufficient if the functions corresponding to the plurality of protocols employed by users are provided at and only at the subscriber switches which directly serve those users, whereby the hardware configuration of the transit switches etc. can be simplified. In addition, bandwidth can be allocated with high precision.

摘要翻译： 当ATM网络中的带宽被控制以便根据用户请求增加时，存在从请求的发生到实际改变带宽的相当大的延迟; 因此需要更快更灵活地控制在ATM网络传输路径中流动的业务。 当决定是否接受带宽改变请求时，还需要降低超额预定发生的概率。 因此，包含与剩余带宽有关的信息的路由信息​​因此由为终端服务的用户交换机提前收集。 响应于来自用户的请求，用户交换机单独地应答快速。 在该过程中，考虑在相同残余带宽测量周期内存在多个带​​宽改变请求的事实，并且为其他带宽改变请求保留测量的剩余带宽的一部分。 这样可以缩短延迟。 此外，只要在用户交换机上只提供与用户所采用的多种协议相对应的功能，就可以简化直接用于这些用户的用户交换机，从而可以简化转接交换机的硬件配置。 此外，可以高精度地分配带宽。

公开(公告)号：US5469543A

公开(公告)日：1995-11-21

申请号：US931039

申请日：1992-08-14

申请人： Motoo Nishihara ,  Takatoshi Kurano ,  Naoaki Yamanaka ,  Youichi Sato

发明人： Motoo Nishihara ,  Takatoshi Kurano ,  Naoaki Yamanaka ,  Youichi Sato

IPC分类号： H04Q11/04 ,  H04L12/813 ,  H04L12/823 ,  H04L12/863 ,  H04Q3/00 ,  G06F7/02 ,  G06F7/04 ,  G06F7/10

CPC分类号： H04L12/5602 ,  H04L49/309 ,  H04L2012/5614 ,  H04L2012/5619 ,  H04L2012/5636

摘要： In a policing arrangement for an ATM network, every incoming cell is stored in a cell buffer and a virtual path identifier (VPI) contained in the cell is extracted and translated to a corresponding one of a set of threshold values. Policing circuits of a matrix array are connected column by column for transferring a VPI in accordance with a read/write control circuit. Each policing circuit of the first column is uniquely responsive to a VPI of a particular value for storing the extracted VPI into a bridge memory, and this column has a greater number of policing circuits than any of the other columns of the array. In each column of the array, at least one of the policing circuits includes a cell counter for incrementing a cell count value in response to the VPI of every incoming cell and decrementing the cell count in response to a VPI read out of the bridge memory of the policing circuit. The cell count value is compared with the threshold value and a cell is discarded from the cell buffer when the cell count value exceeds the threshold value.

摘要翻译： 在ATM网络的监管安排中，每个传入小区被存储在小区缓冲器中，并且包含在小区中的虚拟路径标识符（VPI）被提取并转换成一组阈值中的对应的一个。 矩阵阵列的监控电路逐列连接，以便根据读/写控制电路传输VPI。 第一列的每个监管电路唯一地响应用于将提取的VPI存储到桥接存储器中的特定值的VPI，并且该列具有比阵列的任何其他列中更多数量的监管电路。 在阵列的每一列中，至少一个监管电路包括一个单元计数器，用于响应于每个输入单元的VPI递增单元计数值，并响应于桥接器读出的VPI而递减单元计数 监管电路。 将小区计数值与阈值进行比较，并且当小区计数值超过阈值时，从小区缓冲器中丢弃小区。

公开(公告)号：US5432713A

公开(公告)日：1995-07-11

申请号：US996897

申请日：1992-12-28

申请人： Hiroshi Takeo ,  Michio Kusayanagi ,  Kazuo Iguchi ,  Naoaki Yamanaka ,  Youichi Sato

发明人： Hiroshi Takeo ,  Michio Kusayanagi ,  Kazuo Iguchi ,  Naoaki Yamanaka ,  Youichi Sato

IPC分类号： H04L12/54 ,  H04L12/70 ,  G04F5/00 ,  G08C19/00 ,  H04J3/16

CPC分类号： H04L12/5602 ,  H04L2012/5636

摘要： A usage parameter control circuit for effecting a policing control in an ATM transmission network, comprising a time interval measuring unit for measuring a time interval between a current arrival time of a cell to be judged, and an arrival time of a cell which arrived a reference threshold number of cells before the currently arriving cell arrives; and a judging unit for judging whether or not the measured time interval is shorter than a reference threshold time interval, whereby a longer accessing time is allowed and the circuit construction has a flexible expandability.

摘要翻译： 一种用于实现ATM传输网络中的监管控制的使用参数控制电路，包括：时间间隔测量单元，用于测量待判断小区的当前到达时间与到达参考的小区的到达时间之间的时间间隔; 当前到达的小区到达之前的小区的阈值数目; 以及判断单元，用于判断测量的时间间隔是否短于参考阈值时间间隔，从而允许更长的访问时间，并且电路结构具有灵活的可扩展性。

公开(公告)号：US08488964B2

公开(公告)日：2013-07-16

申请号：US13054876

申请日：2009-07-03

申请人： Naoaki Yamanaka ,  Yutaka Arakawa ,  Kazumasa Tokuhashi

发明人： Naoaki Yamanaka ,  Yutaka Arakawa ,  Kazumasa Tokuhashi

IPC分类号： H04B10/20 ,  H04J14/00

CPC分类号： H04Q11/0067 ,  H04L12/2869 ,  H04Q2011/0041 ,  H04Q2011/0064 ,  H04Q2011/0079 ,  H04Q2011/0088

摘要： In an access network using optical switches, communications between an OLT and ONUs are established without a photoelectric conversion performed at an optical switching unit.The OLT controls the downlink optical switch SW(DOWN) to sequentially select each ONU in slots arranged in a discrete manner, and transmits a Discovery Gate message. Upon receipt of the Discovery Gate message, each ONU consecutively transmits Register Request messages. The uplink optical switch SW(UP) sequentially switch signals from ONU#1 through ONU#128 in the slots arranged in a discrete manner, and outputs the signals to the OLT, Some of the Register Requests transmitted from the respective ONUs pass through the SW(UP), and reach the OLT. Based on the received Register Requests, the OLT determines the timing of transmission for the ONUS, and notifies the ONUS of the timing of transmission through a Gate message.

摘要翻译： 在使用光交换机的接入网络中，OLT和ONU之间的通信建立，而不在光开关单元处执行光电转换。 OLT控制下行光纤交换机SW（DOWN），以离散方式排列的时隙顺序选择每个ONU，并发送发现门信息。 在接收到发现门消息时，每个ONU连续发送注册请求消息。 上行链路光开关SW（UP）以离散方式顺序地切换来自ONU＃1至ONU＃128的信号，并将该信号输出到OLT，从各个ONU发送的一些寄存器请求通过SW （UP），并到达OLT。 根据收到的注册请求，OLT确定ONUS的传输时序，并通过Gate消息向ONUS通知传输的定时。

公开(公告)号：US5828654A

公开(公告)日：1998-10-27

申请号：US653475

申请日：1996-05-24

申请人： Akihiko Takase ,  Shigeo Shinada ,  Mitsuhiro Takano ,  Toshiya Oouchi ,  Naoaki Yamanaka ,  Youichi Sato

发明人： Akihiko Takase ,  Shigeo Shinada ,  Mitsuhiro Takano ,  Toshiya Oouchi ,  Naoaki Yamanaka ,  Youichi Sato

IPC分类号： H04L12/813 ,  H04Q11/04 ,  H04J3/14

CPC分类号： H04L12/5602 ,  H04L49/3081 ,  H04Q11/0478 ,  H04L2012/5636 ,  H04L2012/5651

摘要： In an input cell policing method in a network of an asynchronous transfer mode, according to information contained in a header field of each input cell, a group to which the cell belongs is identified. For each group, there are set a plurality of time frames having a predetermined length and mutually different phases to count the number of input cells in each time frame period. For each time frame, the count value of input cells is compared with a predetermined threshold value. An input cell for which the count value exceeds the threshold value in either one of the time frames is assumed to be an excess cell. The excess cell is discarded or a violation mark is added thereto.

摘要翻译： 在异步传输模式的网络中的输入单元监管方法中，根据包含在每个输入单元的报头字段中的信息，识别该单元所属的组。 对于每个组，设置具有预定长度和相互不同相位的多个时间帧以对每个时间段中的输入单元的数量进行计数。 对于每个时间帧，将输入单元的计数值与预定阈值进行比较。 在任一时间帧中计数值超过阈值的输入单元被假设为过剩单元。 丢弃多余的单元格或向其中添加违规标记。

公开(公告)号：US5509008A

公开(公告)日：1996-04-16

申请号：US205886

申请日：1994-03-03

申请人： Kouichi Genda ,  Naoaki Yamanaka

发明人： Kouichi Genda ,  Naoaki Yamanaka

IPC分类号： H04L12/54 ,  H04L12/70 ,  H04L12/933 ,  H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/1576 ,  H04L2012/5605 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04L2012/5681 ,  H04L2012/5682

摘要： An ATM switch in which the throughput is improved by the simplified arbitration scheme and circuit configuration. This ATM switch uses a matrix type switch formed by N input lines for transmitting the cells read out from the input buffers, M output lines for transmitting the cells to be written into the output buffers, and N.times.M crosspoints located at intersections of the input lines and the output lines, where each crosspoint at an intersection of one input line and one output line carries out an arbitration operation in which a cell arriving from an upper stream side of that one output line is passed to a lower stream side of that one output line with a higher priority than a cell arriving from that one input line, and tile cell arriving from that one input line is transferred to the lower stream side of that one output line only when there is no cell arriving from the upper stream side of that one output line.

摘要翻译： 一种ATM交换机，其中通过简化的仲裁方案和电路配置来提高吞吐量。 该ATM交换机使用由N条输入线构成的矩阵型开关，用于发送从输入缓冲器读出的单元，将用于发送要写入的单元的M条输出线输出到输出缓冲器;以及NxM交叉点，位于输入线和 输出线，其中在一个输入线和一个输出线的交叉点处的每个交叉点执行仲裁操作，其中从该一条输出线的上游侧到达的信元被传递到该一条输出线的下游侧 具有比从该一条输入线到达的小区更高的优先权，并且仅当没有从该一条输入线的上游侧到达的小区时，从该一条输入线到达的瓦砾单元被传送到该一条输出线的下游侧 输出线。