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    Security chip architecture and implementations for cryptography acceleration
    41.
    发明授权
    Security chip architecture and implementations for cryptography acceleration 有权
    安全芯片架构和密码加速实现

    公开(公告)号：US06477646B1

    公开(公告)日：2002-11-05

    申请号：US09510486

    申请日：2000-02-23

    申请人： Suresh Krishna ,  Christopher Owen

    发明人： Suresh Krishna ,  Christopher Owen

    IPC分类号： H04L932

    CPC分类号： G06F9/3879 ,  G06F21/72 ,  G06F2207/7219 ,  H04L63/0485 ,  H04L63/123 ,  H04L63/164 ,  H04L69/12

    摘要： An architecture and a method for a cryptography acceleration is disclosed that allows significant performance improvements without the use of external memory. Specifically, the chip architecture enables “cell-based” processing of random-length IP packets. The IP packets, which may be of variable and unknown size, are split into fixed-size “cells.” The fixed-sized cells are then processed and reassembled into packets. The cell-based packet processing architecture of the present invention allows the implementation of a processing pipeline that has known processing throughput and timing characteristics, thus making it possible to fetch and process the cells in a predictable time frame. The architecture is scalable and is also independent of the type of cryptography performed. The cells may be fetched ahead of time (pre-fetched) and the pipeline may be staged in such a manner that attached (local) memory is not required to store packet data or control parameters.

    摘要翻译： 公开了一种用于加密加速的架构和方法，其允许在不使用外部存储器的情况下进行显着的性能改进。 具体来说，芯片架构使得能够对随机长度的IP分组进行“基于小区的”处理。 可能是未知大小的IP数据包被拆分为固定大小的“单元格”。 然后将固定大小的小区处理并重新组装成分组。 本发明的基于小区的分组处理架构允许实现具有已知处理吞吐量和定时特性的处理流水线，从而使得可以在可预测的时间帧中获取和处理小区。 该架构是可扩展的，并且也独立于执行的加密类型。 可以提前提取单元（预取），并且流水线可以以不需要附加（本地）存储器来存储分组数据或控制参数的方式进行。

    Security chip architecture and implementations for cryptography acceleration
    42.
    发明授权
    Security chip architecture and implementations for cryptography acceleration 有权
    安全芯片架构和密码加速实现

    公开(公告)号：US06971006B2

    公开(公告)日：2005-11-29

    申请号：US10227491

    申请日：2002-08-23

    申请人： Suresh Krishna ,  Christopher Owen

    发明人： Suresh Krishna ,  Christopher Owen

    IPC分类号： G06F1/00 ,  G06F9/38 ,  G06F21/00 ,  H04L9/00

    CPC分类号： G06F9/3879 ,  G06F21/72 ,  G06F2207/7219 ,  H04L63/0485 ,  H04L63/123 ,  H04L63/164 ,  H04L69/12

    摘要： An architecture and a method for a cryptography acceleration is disclosed that allows significant performance improvements without the use of external memory. Specifically, the chip architecture enables “cell-based” processing of random-length IP packets. The IP packets, which may be of variable and unknown size, are split into fixed-size “cells.” The fixed-sized cells are then processed and reassembled into packets. The cell-based packet processing architecture of the present invention allows the implementation of a processing pipeline that has known processing throughput and timing characteristics, thus making it possible to fetch and process the cells in a predictable time frame. The architecture is scalable and is also independent of the type of cryptography performed. The cells may be fetched ahead of time (pre-fetched) and the pipeline may be staged in such a manner that attached (local) memory is not required to store packet data or control parameters.

    摘要翻译： 公开了一种用于加密加速的架构和方法，其允许在不使用外部存储器的情况下进行显着的性能改进。 具体来说，芯片架构使得能够对随机长度的IP分组进行“基于小区的”处理。 可能是未知大小的IP数据包被拆分为固定大小的“单元格”。 然后将固定大小的小区处理并重新组装成分组。 本发明的基于小区的分组处理架构允许实现具有已知处理吞吐量和定时特性的处理流水线，从而使得可以在可预测的时间帧中获取和处理小区。 该架构是可扩展的，并且也独立于执行的加密类型。 可以提前提取单元（预取），并且流水线可以以不需要附加（本地）存储器来存储分组数据或控制参数的方式进行。

    Video stabilization
    44.
    发明授权
    Video stabilization 有权
    视频稳定

    公开(公告)号：US08723966B2

    公开(公告)日：2014-05-13

    申请号：US13307800

    申请日：2011-11-30

    申请人： Christopher Owen ,  Pontus Carlsson

    发明人： Christopher Owen ,  Pontus Carlsson

    IPC分类号： H04N5/228

    CPC分类号： H04N5/23251 ,  H04N5/23258 ,  H04N5/23264 ,  H04N5/23267 ,  H04N2007/145

    摘要： Method, device and computer program product for transmitting a video signal from a user device includes capturing a plurality of frames of the video signal using a camera at the user device, determining a functional state of the device and selectively stabilizing the video signal prior to transmission based on the functional state.

    摘要翻译： 用于从用户设备发送视频信号的方法，设备和计算机程序产品包括在用户设备处使用摄像机捕获视频信号的多个帧，确定设备的功能状态并在传输之前选择性地稳定视频信号 基于功能状态。

    Video Stabilization
    46.
    发明申请
    Video Stabilization 有权
    视频稳定

    公开(公告)号：US20130076921A1

    公开(公告)日：2013-03-28

    申请号：US13307800

    申请日：2011-11-30

    申请人： Christopher Owen ,  Pontus Carlsson

    发明人： Christopher Owen ,  Pontus Carlsson

    IPC分类号： H04N5/228

    CPC分类号： H04N5/23251 ,  H04N5/23258 ,  H04N5/23264 ,  H04N5/23267 ,  H04N2007/145

    摘要： Method, device and computer program product for transmitting a video signal from a user device includes capturing a plurality of frames of the video signal using a camera at the user device, determining a functional state of the device and selectively stabilizing the video signal prior to transmission based on the functional state.

    摘要翻译： 用于从用户设备发送视频信号的方法，设备和计算机程序产品包括在用户设备处使用摄像机捕获视频信号的多个帧，确定设备的功能状态并在传输之前选择性地稳定视频信号 基于功能状态。

    Security chip architecture and implementations for cryptography acceleration
    47.
    发明授权
    Security chip architecture and implementations for cryptography acceleration 有权
    安全芯片架构和密码加速实现

    公开(公告)号：US07124296B2

    公开(公告)日：2006-10-17

    申请号：US11229457

    申请日：2005-09-16

    申请人： Suresh Krishna ,  Christopher Owen

    发明人： Suresh Krishna ,  Christopher Owen

    IPC分类号： H04L9/00 ,  H04L9/32

    CPC分类号： G06F9/3879 ,  G06F21/72 ,  G06F2207/7219 ,  H04L63/0485 ,  H04L63/123 ,  H04L63/164 ,  H04L69/12

    摘要： An architecture and a method for cryptography acceleration is disclosed that allows significant performance improvements without the use of external memory. Specifically, the chip architecture enables “cell-based” processing of random-length IP packets. The IP packets, which may be of variable and unknown size, are split into fixed size “cells.” The fixed-size cells are then processed and reassembled into packets. The cell-based packet processing architeture of the present invention allows the implementation of a processing pipeline that has known processing throughput and timing characteristics, thus making it possible to fetch and process the cells in a predictable time frame. The architecture is scalable and is also independent of the type of cryptography performed. The cells may be fetched ahead of time (pre-fetched) and the pipeline may be staged in such a manner that attached (local) memory is not required to store packet or control parameters.

    摘要翻译： 公开了一种用于加密加速的架构和方法，其允许在不使用外部存储器的情况下进行显着的性能改进。 具体来说，芯片架构使得能够对随机长度的IP分组进行“基于小区的”处理。 可能是未知大小的IP数据包被拆分成固定大小的“单元格”。 然后对固定大小的单元进行处理并将其重新组装成包。 本发明的基于小区的分组处理架构允许实现具有已知处理吞吐量和定时特性的处理流水线，从而使得可以在可预测的时间帧中获取和处理小区。 该架构是可扩展的，并且也独立于执行的加密类型。 可以提前提取单元（预取），并且管道可以以不需要附加（本地）存储器来存储分组或控制参数的方式进行。

    Classification engine in a cryptography acceleration chip
    48.
    发明授权
    Classification engine in a cryptography acceleration chip 有权
    密码加速芯片中的分类引擎

    公开(公告)号：US07996670B1

    公开(公告)日：2011-08-09

    申请号：US09610722

    申请日：2000-07-06

    申请人： Suresh Krishna ,  Christopher Owen ,  Derrick C. Lin ,  Joseph J. Tardo ,  Patrick Law ,  Phillip Norman Smith

    发明人： Suresh Krishna ,  Christopher Owen ,  Derrick C. Lin ,  Joseph J. Tardo ,  Patrick Law ,  Phillip Norman Smith

    IPC分类号： H04L29/00

    CPC分类号： H04L63/0428 ,  G06F9/3879 ,  G06F21/604 ,  G06F21/72 ,  G06F2207/7219 ,  H04L63/0485 ,  H04L63/164

    摘要： Provided is an architecture for a cryptography accelerator chip that allows significant performance improvements over previous prior art designs. In various embodiments, the architecture enables parallel processing of packets through a plurality of cryptography engines and includes a classification engine configured to efficiently process encryption/decryption of data packets. Cryptography acceleration chips in accordance may be incorporated on network line cards or service modules and used in applications as diverse as connecting a single computer to a WAN, to large corporate networks, to networks servicing wide geographic areas (e.g., cities). The present invention provides improved performance over the prior art designs, with much reduced local memory requirements, in some cases requiring no additional external memory. In some embodiments, the present invention enables sustained full duplex Gigabit rate security processing of IPSec protocol data packets.

    摘要翻译： 提供了一种用于加密加速器芯片的架构，其允许比先前的现有技术设计显着的性能改进。 在各种实施例中，架构能够通过多个密码引擎并行处理分组，并且包括被配置为有效地处理数据分组的加密/解密的分类引擎。 密码学加速芯片可以被合并在网络线卡或服务模块上，并用于将单个计算机连接到WAN，大型企业网络以及服务于广泛地理区域（例如，城市）的网络的应用。 本发明提供了相对于现有技术设计的改进的性能，其中局部存储器要求大大降低，在某些情况下不需要额外的外部存储器。 在一些实施例中，本发明实现IPSec协议数据分组的持续全双工千兆比特速率安全处理。

    Security chip architecture and implementations for cryptography acceleration
    50.
    发明申请
    Security chip architecture and implementations for cryptography acceleration 有权

    公开(公告)号：US20060021022A1

    公开(公告)日：2006-01-26

    申请号：US11229457

    申请日：2005-09-16

    申请人： Suresh Krishna ,  Christopher Owen

    发明人： Suresh Krishna ,  Christopher Owen

    IPC分类号： G06F15/16

    CPC分类号： G06F9/3879 ,  G06F21/72 ,  G06F2207/7219 ,  H04L63/0485 ,  H04L63/123 ,  H04L63/164 ,  H04L69/12

    摘要： An architecture and a method for cryptography acceleration is disclosed that allows significant performance improvements without the use of external memory. Specifically, the chip architecture enables “cell-based” processing of random-length IP packets. The IP packets, which may be of variable and unknown size, are split into fixed size “cells.” The fixed-size cells are then processed and reassembled into packets. The cell-based packet processing architeture of the present invention allows the implementation of a processing pipeline that has known processing throughput and timing characteristics, thus making it possible to fetch and process the cells in a predictable time frame. The architecture is scalable and is also independent of the type of cryptography performed. The cells may be fetched ahead of time (pre-fetched) and the pipeline may be staged in such a manner that attached (local) memory is not required to store packet or control parameters.