公开(公告)号：US20150021702A1

公开(公告)日：2015-01-22

申请号：US13947439

申请日：2013-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Johannes M. van Meer ,  Xiaodong Yang ,  Manfred J. Eller

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/30625 ,  H01L21/31053 ,  H01L29/0653 ,  H01L29/7846

Abstract: A semiconductor structure with an improved shallow trench isolation (STI) region and method of fabrication is disclosed. The STI region comprises a lower portion filled with oxide and an upper portion comprising a high Young's modulus (HYM) liner disposed on the lower portion and trench sidewalls and filled with oxide. The HYM liner is disposed adjacent to source-drain regions, and serves to reduce stress relaxation within the shallow trench isolation (STI) oxide, which has a relatively low Young's modulus and is soft. Hence, the HYM liner serves to increase the desired stress imparted by the embedded stressor source-drain regions, which enhances carrier mobility, thus increasing semiconductor performance.

Abstract translation: 公开了具有改进的浅沟槽隔离（STI）区域和制造方法的半导体结构。 STI区域包括填充有氧化物的下部分和包括设置在下部分上的高杨氏模量（HYM）衬垫和沟槽侧壁并填充有氧化物的上部部分。 HYM衬垫设置在源 - 漏区附近，用于减少浅沟槽隔离（STI）氧化物中的应力松弛，其具有较低的杨氏模量并且柔软。 因此，HYM衬垫用于增加由嵌入式应力源源极 - 漏极区域施加的所需应力，这增强了载流子迁移率，从而提高了半导体性能。

公开(公告)号：US20140302660A1

公开(公告)日：2014-10-09

申请号：US13856542

申请日：2013-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Jerome Ciavatti

IPC: H01L21/768 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76895 ,  H01L27/0255

Abstract: Embodiments disclosed describe approaches for providing a local interconnection between a protection diode and a gate transistor in an integrated circuit (IC) device. Specifically, described is an IC device comprising: a protection diode formed in a substrate, a replacement metal gate (RMG) transistor formed over the substrate, a first contact formed over the protection diode (and optional trench silicide layer), a second contact formed over the RMG transistor, wherein the first contact extends to connect directly with the second contact, and a top metal layer (M1) formed over the first contact and the second contact. By extending the first contact from the protection diode directly to the gate transistor as a supplemental interconnect, any charges accumulated during formation of the second contact and the set of vias will be discharged by the protection diode.

Abstract translation: 公开的实施例描述了在集成电路（IC）装置中提供保护二极管和栅极晶体管之间的局部互连的方法。 具体地，描述了一种IC器件，包括：形成在衬底中的保护二极管，在衬底上形成的替代金属栅极（RMG）晶体管，形成在保护二极管（和可选的沟槽硅化物层）上方的第一接触，形成的第二接触 在所述RMG晶体管上，其中所述第一触点延伸以直接与所述第二触点连接，以及形成在所述第一触点和所述第二触点上的顶部金属层（M1）。 通过将第一接触从保护二极管直接延伸到栅极晶体管作为补充互连，在形成第二接触和通孔组期间累积的任何电荷将被保护二极管放电。

公开(公告)号：US20140103420A1

公开(公告)日：2014-04-17

申请号：US13650233

申请日：2012-10-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanxiang Liu ,  Vara Vakada ,  Jerome Ciavatti

IPC: H01L29/78

CPC classification number: H01L23/5225 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative device disclosed herein includes a transistor comprising a gate electrode and a drain region formed in a semiconducting substrate, an isolation structure formed in the substrate, wherein the isolation structure is laterally positioned between the gate electrode and the drain region, and a Faraday shield that is positioned laterally between the gate electrode and the drain region and above the isolation structure, wherein the Faraday shield has a long axis that is oriented substantially vertically relative to an upper surface of the substrate.

Abstract translation: 本文公开的一种说明性器件包括晶体管，其包括形成在半导体衬底中的栅电极和漏区，形成在衬底中的隔离结构，其中隔离结构横向地位于栅电极和漏区之间，法拉第屏蔽 其位于栅极电极和漏极区域之间并且隔离结构之上，其中法拉第屏蔽具有相对于衬底的上表面基本垂直取向的长轴。