公开(公告)号：US20150348830A1

公开(公告)日：2015-12-03

申请号：US14824361

申请日：2015-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Johannes M. van Meer ,  Xiaodong Yang ,  Manfred J. Eller

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/30625 ,  H01L21/31053 ,  H01L29/0653 ,  H01L29/7846

Abstract: A semiconductor structure with an improved shallow trench isolation (STI) region and method of fabrication is disclosed. The STI region comprises a lower portion filled with oxide and an upper portion comprising a high Young's modulus (HYM) liner disposed on the lower portion and trench sidewalls and filled with oxide. The HYM liner is disposed adjacent to source-drain regions, and serves to reduce stress relaxation within the shallow trench isolation (STI) oxide, which has a relatively low Young's modulus and is soft. Hence, the HYM liner serves to increase the desired stress imparted by the embedded stressor source-drain regions, which enhances carrier mobility, thus increasing semiconductor performance.

公开(公告)号：US09142640B1

公开(公告)日：2015-09-22

申请号：US14306864

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Xiaodong Yang ,  Yanxiang Liu ,  Jin Ping Liu

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: A non-planar transistor is fabricated with dummy or sacrificial epitaxy and a structure for subsequent replacement or final epitaxy containment is created around the sacrificial epitaxy. The dummy epitaxy is then removed and replaced with the replacement epitaxy. The containment structure allows for uniform growth of the replacement epitaxy and prevents merger. Where n-type and p-type structures are present, the replacement epitaxy process is performed for each type, while protecting the other type with a mask. Optionally, one of the replacement epitaxies, i.e., the one for n-type or p-type, may be used as the dummy epitaxy, resulting in the need for only one mask.

Abstract translation: 用虚拟或牺牲外延制造非平面晶体管，并且在牺牲外延周围产生用于后续替换或最终外延容纳的结构。 然后去除虚拟外延并用替换外延代替。 容纳结构允许替代外延的均匀生长并且防止合并。 在存在n型和p型结构的情况下，对于每种类型进行替换外延工艺，同时用掩模保护另一种类型。 任选地，替代的外延（即，用于n型或p型的）中的一种可以用作虚拟外延，导致仅需要一个掩模。

公开(公告)号：US08835292B2

公开(公告)日：2014-09-16

申请号：US13664744

申请日：2012-10-31

Applicant: International Business Machines Corporation ,  Globalfoundries Inc.

Inventor： Michael P. Chudzik ,  Min Dai ,  Xiang Hu ,  Jinping Liu ,  Yanxiang Liu ,  Xiaodong Yang

IPC: H01L21/3205

CPC classification number: H01L29/66545 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462

Abstract: A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

Abstract translation: 公开了一种制造半导体器件的方法，该半导体器件包括结合导电虚拟栅极层（例如硅锗（SiGe），氮化钛等）的替代金属栅极工艺）和相关的方法。 该方法包括在衬底上形成氧化物层; 在所述半导体器件的第一区域中从所述衬底去除所述氧化物层的栅极部分; 在所述第一区域中的所述半导体器件上形成导电虚拟栅极层; 以及在所述半导体器件上形成栅极，所述栅极包括设置在所述第一区域中并直接连接到所述衬底的栅极导体。

公开(公告)号：US20140264613A1

公开(公告)日：2014-09-18

申请号：US13835944

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Xiaodong Yang ,  Jin Ping Liu ,  Yanxiang Liu ,  Xusheng Wu

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a semiconductor substrate includes a shallow trench isolation structure disposed therein. A gate electrode structure overlies semiconductor material of the semiconductor substrate. A first sidewall spacer is formed adjacent to the gate electrode structure, with a first surface of the shallow trench isolation structure exposed and spaced from the first sidewall spacer by a region of the semiconductor material. The first surface of the shallow trench isolation structure is masked with an isolation structure mask. The region of the semiconductor material is free from the isolation structure mask. A recess is etched in the region of the semiconductor material, with the isolation structure mask in place. A semiconductor material is epitaxially grown within the recess to form an epitaxially-grown semiconductor region adjacent to the gate electrode structure.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，半导体衬底包括设置在其中的浅沟槽隔离结构。 栅电极结构覆盖半导体衬底的半导体材料。 形成与栅电极结构相邻的第一侧壁间隔物，其中浅沟槽隔离结构的第一表面暴露并与第一侧壁间隔物隔开半导体材料的区域。 浅沟槽隔离结构的第一表面用隔离结构掩模掩蔽。 半导体材料的区域没有隔离结构掩模。 在半导体材料的区域中蚀刻凹陷，隔离结构掩模就位。 半导体材料在凹槽内外延生长以形成与栅电极结构相邻的外延生长的半导体区域。

公开(公告)号：US20140159052A1

公开(公告)日：2014-06-12

申请号：US13710639

申请日：2012-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinping Liu ,  Yi Qi ,  Xiaodong Yang

IPC: H01L29/78 ,  H01L21/02

CPC classification number: H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: Embodiments of the invention provide an improved method and structure for a transistor with reduced DIBL and RON. A sigma cavity is formed in a semiconductor substrate adjacent to a transistor. The sigma cavity is filled with an epitaxially grown semiconductor material that also serves as a stress-inducing region for the purposes of increasing carrier mobility. The epitaxially grown semiconductor material is doped with a reverse doping profile. A lightly doped region lines the interior of the sigma cavity, followed by an undoped region, followed by a heavily doped region. The shape of the lightly doped region is such that it is thicker adjacent to the channel, which reduces RON, and thinner below the channel, which reduces DIBL.

Abstract translation: 本发明的实施例提供了具有减少的DIBL和RON的晶体管的改进的方法和结构。 在与晶体管相邻的半导体衬底中形成Σ腔。 填充有外延生长的半导体材料，其也用作应力诱导区域，以增加载流子迁移率。 外延生长的半导体材料掺杂有反向掺杂分布。 轻掺杂区域将西格玛腔体的内部引导，随后是未掺杂的区域，随后是重掺杂区域。 轻掺杂区域的形状使其在沟道附近较厚，这降低了RON，并且在沟道以下更薄，这降低了DIBL。

公开(公告)号：US20140120708A1

公开(公告)日：2014-05-01

申请号：US13664744

申请日：2012-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Min Dai ,  Xiang Hu ,  Jinping Liu ,  Yanxiang Liu ,  Xiaodong Yang

IPC: H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462

Abstract: A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

Abstract translation: 公开了一种制造半导体器件的方法，该半导体器件包括结合导电虚拟栅极层（例如硅锗（SiGe），氮化钛等）的替代金属栅极工艺）和相关的方法。 该方法包括在衬底上形成氧化物层; 在所述半导体器件的第一区域中从所述衬底去除所述氧化物层的栅极部分; 在所述第一区域中的所述半导体器件上形成导电虚拟栅极层; 以及在所述半导体器件上形成栅极，所述栅极包括设置在所述第一区域中并直接连接到所述衬底的栅极导体。

公开(公告)号：US09419126B2

公开(公告)日：2016-08-16

申请号：US13835944

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xiaodong Yang ,  Jin Ping Liu ,  Yanxiang Liu ,  Xusheng Wu

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/78 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a semiconductor substrate includes a shallow trench isolation structure disposed therein. A gate electrode structure overlies semiconductor material of the semiconductor substrate. A first sidewall spacer is formed adjacent to the gate electrode structure, with a first surface of the shallow trench isolation structure exposed and spaced from the first sidewall spacer by a region of the semiconductor material. The first surface of the shallow trench isolation structure is masked with an isolation structure mask. The region of the semiconductor material is free from the isolation structure mask. A recess is etched in the region of the semiconductor material, with the isolation structure mask in place. A semiconductor material is epitaxially grown within the recess to form an epitaxially-grown semiconductor region adjacent to the gate electrode structure.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，半导体衬底包括设置在其中的浅沟槽隔离结构。 栅电极结构覆盖半导体衬底的半导体材料。 形成与栅电极结构相邻的第一侧壁间隔物，其中浅沟槽隔离结构的第一表面暴露并与第一侧壁间隔物隔开半导体材料的区域。 浅沟槽隔离结构的第一表面用隔离结构掩模掩蔽。 半导体材料的区域没有隔离结构掩模。 在半导体材料的区域中蚀刻凹陷，隔离结构掩模就位。 半导体材料在凹槽内外延生长以形成与栅电极结构相邻的外延生长的半导体区域。

公开(公告)号：US09136330B2

公开(公告)日：2015-09-15

申请号：US13947439

申请日：2013-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Johannes M. van Meer ,  Xiaodong Yang ,  Manfred J. Eller

IPC: H01L29/49 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/30625 ,  H01L21/31053 ,  H01L29/0653 ,  H01L29/7846

Abstract: A semiconductor structure with an improved shallow trench isolation (STI) region and method of fabrication is disclosed. The STI region comprises a lower portion filled with oxide and an upper portion comprising a high Young's modulus (HYM) liner disposed on the lower portion and trench sidewalls and filled with oxide. The HYM liner is disposed adjacent to source-drain regions, and serves to reduce stress relaxation within the shallow trench isolation (STI) oxide, which has a relatively low Young's modulus and is soft. Hence, the HYM liner serves to increase the desired stress imparted by the embedded stressor source-drain regions, which enhances carrier mobility, thus increasing semiconductor performance.

Abstract translation: 公开了具有改进的浅沟槽隔离（STI）区域和制造方法的半导体结构。 STI区域包括填充有氧化物的下部分和包括设置在下部分上的高杨氏模量（HYM）衬垫和沟槽侧壁并填充有氧化物的上部部分。 HYM衬垫设置在源 - 漏区附近，用于减少浅沟槽隔离（STI）氧化物中的应力松弛，其具有较低的杨氏模量并且柔软。 因此，HYM衬垫用于增加由嵌入式应力源源极 - 漏极区域施加的所需应力，这增强了载流子迁移率，从而提高了半导体性能。

公开(公告)号：US20150021702A1

公开(公告)日：2015-01-22

申请号：US13947439

申请日：2013-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Johannes M. van Meer ,  Xiaodong Yang ,  Manfred J. Eller

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/30625 ,  H01L21/31053 ,  H01L29/0653 ,  H01L29/7846

Abstract: A semiconductor structure with an improved shallow trench isolation (STI) region and method of fabrication is disclosed. The STI region comprises a lower portion filled with oxide and an upper portion comprising a high Young's modulus (HYM) liner disposed on the lower portion and trench sidewalls and filled with oxide. The HYM liner is disposed adjacent to source-drain regions, and serves to reduce stress relaxation within the shallow trench isolation (STI) oxide, which has a relatively low Young's modulus and is soft. Hence, the HYM liner serves to increase the desired stress imparted by the embedded stressor source-drain regions, which enhances carrier mobility, thus increasing semiconductor performance.

Abstract translation: 公开了具有改进的浅沟槽隔离（STI）区域和制造方法的半导体结构。 STI区域包括填充有氧化物的下部分和包括设置在下部分上的高杨氏模量（HYM）衬垫和沟槽侧壁并填充有氧化物的上部部分。 HYM衬垫设置在源 - 漏区附近，用于减少浅沟槽隔离（STI）氧化物中的应力松弛，其具有较低的杨氏模量并且柔软。 因此，HYM衬垫用于增加由嵌入式应力源源极 - 漏极区域施加的所需应力，这增强了载流子迁移率，从而提高了半导体性能。