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公开(公告)号：US20200160809A1
公开(公告)日：2020-05-21
申请号：US16685388
申请日：2019-11-15
Applicant: Google LLC
Inventor： Albert Meixner , Neeti Desai , Dilan Manatunga , Jason Rupert Redgrave , William R. Mark
Abstract: An image processor is described. The image processor includes an I/O unit to read input image data from external memory for processing by the image processor and to write output image data from the image processor into the external memory. The I/O unit includes multiple logical channel units. Each logical channel unit is to form a logical channel between the external memory and a respective producing or consuming component within the image processor. Each logical channel unit is designed to utilize reformatting circuitry and addressing circuitry. The addressing circuitry is to control addressing schemes applied to the external memory and reformatting of image data between external memory and the respective producing or consuming component. The reformatting circuitry is to perform the reformatting.
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公开(公告)号：US10552939B1
公开(公告)日：2020-02-04
申请号：US16273663
申请日：2019-02-12
Applicant: Google LLC
Inventor： Albert Meixner
Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for supporting complex transfer functions on an image processor. One of the methods includes traversing, by each execution lane of an image processor using a shift-register array, a respective local support region and storing input pixels encountered during the traversal into local memory of the image processor. Each execution lane obtains from the local memory of the image processor one or more input pixels according to a complex transfer function. Each execution lane computes a respective output pixel for the kernel program using one or more input pixels obtained from the local memory according to the complex transfer function.
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公开(公告)号：US10481870B2
公开(公告)日：2019-11-19
申请号：US15594223
申请日：2017-05-12
Applicant: Google LLC
Inventor： Artem Vasilyev , Albert Meixner , Jason Redgrave
Abstract: An execution unit is described. The execution unit includes an arithmetic logic unit (ALU) circuit having a first input to receive a first value and a second input to receive a second value. The ALU circuit includes circuitry to determine an absolute value of the first value and to add the absolute value to the second value. The first input is coupled to a first data path having register space and an output of another ALU of the execution unit circuit as alternative sources of the first value. The second input is coupled to a second data path having the register space as a source for the second value.
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公开(公告)号：US10430919B2
公开(公告)日：2019-10-01
申请号：US15594512
申请日：2017-05-12
Applicant: Google LLC
Inventor： Hyunchul Park , Albert Meixner , Qiuling Zhu , William Mark
IPC: G06F17/50 , G06T1/60 , G06T1/20 , G06F3/06 , G09G5/36 , G06F9/50 , G06F12/084 , G06F12/0842
Abstract: A method is described. The method includes simulating execution of an image processing application software program. The simulating includes intercepting kernel-to-kernel communications with simulated line buffer memories that store and forward lines of image data communicated from models of producing kernels to models of consuming kernels. The simulating further includes tracking respective amounts of image data stored in the respective line buffer memories over a simulation runtime. The method also includes determining respective hardware memory allocations for corresponding hardware line buffer memories from the tracked respective amounts of image data. The method also includes generating configuration information for an image processor to execute the image processing application software program. The configuration information describes the hardware memory allocations for the hardware line buffer memories of the image processor.
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公开(公告)号：US20190238758A1
公开(公告)日：2019-08-01
申请号：US16376479
申请日：2019-04-05
Applicant: Google LLC
Inventor： Qiuling Zhu , Ofer Shacham , Jason Rupert Redgrave , Daniel Frederic Finchelstein , Albert Meixner
Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.
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Patent Agency Ranking
公开(公告)号：US20190213006A1
公开(公告)日：2019-07-11
申请号：US16251887
申请日：2019-01-18
Applicant: Google LLC
Inventor： Artem Vasilyev , Jason Rupert Redgrave , Albert Meixner , Ofer Shacham
CPC classification number: G06F9/3001 , G06F7/57 , G06F9/30014 , G06F15/80
Abstract: An apparatus is described that includes an execution unit having a multiply add computation unit, a first ALU logic unit and a second ALU logic unit. The ALU unit is to perform first, second, third and fourth instructions. The first instruction is a multiply add instruction. The second instruction is to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction. The third instruction is to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction. The fourth instruction is to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate during to determine first and second division resultant digit values.
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公开(公告)号：US10334194B2
公开(公告)日：2019-06-25
申请号：US15946095
申请日：2018-04-05
Applicant: Google LLC
Inventor： Albert Meixner , Daniel Frederic Finchelstein , David Patterson , William R. Mark , Jason Rupert Redgrave , Ofer Shacham
Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.
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公开(公告)号：US11544060B2
公开(公告)日：2023-01-03
申请号：US17169814
申请日：2021-02-08
Applicant: Google LLC
Inventor： Albert Meixner
Abstract: An image processor is described. The image processor includes a two dimensional shift register array that couples certain ones of its array locations to support execution of a shift instruction. The shift instruction is to include mask information. The mask information is to specify which of the array locations are to be written to with information being shifted. The two dimensional shift register array includes masking logic circuitry to write the information being shifted into specified ones of the array locations in accordance with the mask information.
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公开(公告)号：US11250537B2
公开(公告)日：2022-02-15
申请号：US16694335
申请日：2019-11-25
Applicant: Google LLC
Inventor： Fabrizio Basso , Edward Chang , Daniel Finchelstein , Timothy Knight , William Mark , Albert Meixner , Shahriar Rabii , Jason Redgrave , Masumi Reynders , Ofer Shacham , Don Stark , Michelle Tomasko
Abstract: An image processor unit is described. The image processor unit includes a plurality of inputs to receive at least one input image. The image processor unit includes a plurality of outputs to provide at least one output image. The image processor unit includes a network coupled to the plurality of inputs and the plurality of outputs. The network is to couple at least one of the inputs to at least one of the outputs. The image processor unit includes an image processor circuit coupled to the network. The network to route an input image that is received at one of the inputs to the image processor circuit. The image processor circuit is to execute image signal processing program code to generate a processed output image from the input image. The network is to route the processed output image to at least one of the outputs.
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公开(公告)号：US11030005B2
公开(公告)日：2021-06-08
申请号：US16657656
申请日：2019-10-18
Applicant: Google LLC
Inventor： Hyunchul Park , Albert Meixner
Abstract: A method is described. The method includes calculating data transfer metrics for kernel-to-kernel connections of a program having a plurality of kernels that is to execute on an image processor. The image processor includes a plurality of processing cores and a network connecting the plurality of processing cores. Each of the kernel-to-kernel connections include a producing kernel that is to execute on one of the processing cores and a consuming kernel that is to execute on another one of the processing cores. The consuming kernel is to operate on data generated by the producing kernel. The method also includes assigning kernels of the plurality of kernels to respective ones of the processing cores based on the calculated data transfer metrics.
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