公开(公告)号：US20110161587A1

公开(公告)日：2011-06-30

申请号：US12649548

申请日：2009-12-30

申请人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey Stuecheli ,  Derek E. Williams

发明人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey Stuecheli ,  Derek E. Williams

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0815

摘要： According to a method of data processing, a memory controller receives a plurality of data prefetch requests from multiple processor cores in the data processing system, where the plurality of prefetch load requests include a data prefetch request issued by a particular processor core among the multiple processor cores. In response to receipt of the data prefetch request, the memory controller provides a coherency response indicating an excess number of data prefetch requests. In response to the coherency response, the particular processor core reduces a rate of issuance of data prefetch requests.

摘要翻译： 根据数据处理的方法，存储器控制器从数据处理系统中的多个处理器核心接收多个数据预取请求，其中多个预取负载请求包括由多处理器中的特定处理器核发出的数据预取请求 核心。 响应于接收到数据预取请求，存储器控制器提供指示多余数据预取请求的一致性响应。 响应于一致性响应，特定处理器核心降低了数据预取请求的发布速率。

公开(公告)号：US09189403B2

公开(公告)日：2015-11-17

申请号：US12650018

申请日：2009-12-30

申请人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey Stuecheli ,  Derek E. Williams ,  Thomas R. Puzak

发明人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey Stuecheli ,  Derek E. Williams ,  Thomas R. Puzak

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0811 ,  G06F12/12

摘要： A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.

摘要翻译： 数据处理系统包括第一和第二处理单元和系统存储器。 第一处理单元具有第一上层和第一下层高速缓存，第二处理单元具有第二上层和下层高速缓存。 响应于数据请求，选择要从第一较低级高速缓存丢弃的受害者高速缓存行，并且第一较低级高速缓存选择在执行到第二低级高速缓存的受害者高速缓存行的横向流出（LCO） 基于与受害者高速缓存行相关联的置信指示，将受害者缓存行的丢弃发送到系统存储器。 响应于选择LCO，第一处理单元在互连结构上发布LCO命令，并从第一低级缓存中移除受害者高速缓存行，并且第二下级缓存保存受害缓存行。

公开(公告)号：US20080091905A1

公开(公告)日：2008-04-17

申请号：US11951735

申请日：2007-12-06

申请人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

发明人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G06F13/1626

摘要： Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers while the memory module is busy processing read operations. Then, address-only “write” commands are later issued to write the buffered write data to the memory device. The write commands targeting idle DIMMs are issued in sequence ahead of writes targeting busy DIMMs (or soon to be busy). Moving the data via a background write-to-buffer operation increases the efficiency of the common write data channel and allows the write data bus to reach maximum bandwidth during periods of heavy read activity. The actual write operations, deferred to periods of when the negative affects of the write can be completely/mostly hidden. In periods of light read activity or when there are no reads pending, buffering data in the memory module enables the buffered data to be written in parallel across multiple memory modules simultaneously.

摘要翻译： 内存模块设计有多个写入缓冲器，用于临时保存写入数据。 “写入缓冲”操作将内存控制器中的写入数据移动到写入缓冲区，同时内存模块正忙于处理读取操作。 然后，随后发出仅地址的“写入”命令来将缓冲的写入数据写入存储器件。 针对闲置DIMM的写命令在针对繁忙DIMM（或即将忙于）的写入之前按顺序发出。 通过后台写入缓冲操作移动数据可以提高通用写入数据通道的效率，并允许写入数据总线在重读操作期间达到最大带宽。 实际写入操作，延迟到写入负面影响的时期可以完全/大部分隐藏。 在光读取活动期间，或者当没有读取待处理时，缓冲存储器模块中的数据使缓冲数据能够同时跨多个存储器模块并行编写。

公开(公告)号：US20060179213A1

公开(公告)日：2006-08-10

申请号：US11054447

申请日：2005-02-09

申请人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

发明人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G06F13/1626

摘要： Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers while the memory module is busy processing read operations. Then, address-only “write” commands are later issued to write the buffered write data to the memory device. The write commands targeting idle DIMMs are issued in sequence ahead of writes targeting busy DIMMs (or soon to be busy). Moving the data via a background write-to-buffer operation increases the efficiency of the common write data channel and allows the write data bus to reach maximum bandwidth during periods of heavy read activity. The actual write operations, deferred to periods of when the negative affects of the write can be completely/mostly hidden. In periods of light read activity or when there are no reads pending, buffering data in the memory module enables the buffered data to be written in parallel across multiple memory modules simultaneously.

摘要翻译： 内存模块设计有多个写入缓冲器，用于临时保存写入数据。 “写入缓冲”操作将内存控制器中的写入数据移动到写入缓冲区，同时内存模块正忙于处理读取操作。 然后，随后发出仅地址的“写入”命令来将缓冲的写入数据写入存储器件。 针对闲置DIMM的写命令在针对繁忙DIMM（或即将忙于）的写入之前按顺序发出。 通过后台写入缓冲操作移动数据可以提高通用写入数据通道的效率，并允许写入数据总线在重读操作期间达到最大带宽。 实际写入操作，延迟到写入负面影响的时期可以完全/大部分隐藏。 在光读取活动期间，或者当没有读取待处理时，缓冲存储器模块中的数据使缓冲数据能够同时跨多个存储器模块并行编写。

公开(公告)号：US20060095691A1

公开(公告)日：2006-05-04

申请号：US10922272

申请日：2004-08-19

申请人： Robert Bell ,  Hugh Shen ,  Jeffrey Stuecheli ,  Derek Williams

发明人： Robert Bell ,  Hugh Shen ,  Jeffrey Stuecheli ,  Derek Williams

IPC分类号： G06F12/00

CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F12/0897

摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.

摘要翻译： 处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。 存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。 此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。

公开(公告)号：US20050108605A1

公开(公告)日：2005-05-19

申请号：US09737347

申请日：2000-12-15

申请人： Jeffrey Stuecheli

发明人： Jeffrey Stuecheli

IPC分类号： G01R31/28 ,  G01R31/3183 ,  G06F17/50

CPC分类号： G01R31/318357 ,  G01R31/318307 ,  G01R31/318385 ,  G06F17/5022

摘要： A driver module is provided that generates test patterns with desired tendencies. The driver module provides these test patterns to controlling code for simulation of a hardware model. The test patterns are generated by creating and connecting subgraphs in a Markov chain. The Markov model describes a plurality of states, each having a probability of going to at least one other state. Markov models may be created to determine whether to drive an interface in the hardware model and to determine the command to drive through the interface. Once the driver module creates and connects the subgraphs of the Markov models, the driver module initiates a random walk through the Markov chains and provides the commands to the controlling code.

摘要翻译： 提供了一个驱动程序模块，可以生成具有所需趋势的测试模式。 驱动程序模块提供这些测试模式来控制硬件模型仿真的代码。 测试模式是通过在马尔可夫链中创建和连接子图来生成的。 马尔可夫模型描述了多个状态，每个状态具有进入至少一个其他状态的概率。 可以创建马尔可夫模型来确定是否驱动硬件模型中的接口，并确定通过接口驱动的命令。 一旦驱动程序模块创建并连接马尔科夫模型的子图，驱动程序模块将通过马尔可夫链启动随机游走，并向控制代码提供命令。