公开(公告)号：US20060179183A1

公开(公告)日：2006-08-10

申请号：US11054372

申请日：2005-02-09

申请人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

发明人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  G06F13/161 ,  G11C5/04

摘要： Multiple write buffers are provided within each memory module and are utilized to buffer multiple received write data forwarded to the chip via a write-to-buffer data operation. When a write is received at the memory controller, the memory controller first issues the write-to-buffer (data) operation and the data is forwarded to one of the write buffers. Multiple writes targeting the same DIMM are thus buffered. When all of the available buffers at a memory module are full, the memory controller issues the set of address only write commands to the memory module. The control logic of the DIMM streams all of the buffered write data to the memory device(s) in one continuous burst. By buffering multiple writes and then writing all buffered write data within the DIMM in a single burst, the write-to-read turnaround penalty of the memory module's data bus is substantially minimized.

摘要翻译： 在每个存储器模块内提供多个写入缓冲器，并且用于经由写入缓冲器数据操作来缓冲转发到芯片的多个接收到的写入数据。 当在存储器控制器处接收到写入时，存储器控制器首先发出写入缓冲器（数据）操作，并将数据转发到写入缓冲器之一。 因此，针对同一DIMM的多个写入被缓存。 当内存模块中的所有可用缓冲区都已满时，内存控制器会向内存模块发出一组仅地址写入命令。 DIMM的控制逻辑将所有缓冲的写入数据以一个连续的脉冲串流式传输到存储器件。 通过缓冲多个写入，然后以单个脉冲串将所有缓冲的写入数据写入DIMM内，内存模块的数据总线的写入读取周转损失基本上最小化。

公开(公告)号：US20080091905A1

公开(公告)日：2008-04-17

申请号：US11951735

申请日：2007-12-06

申请人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

发明人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G06F13/1626

摘要： Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers while the memory module is busy processing read operations. Then, address-only “write” commands are later issued to write the buffered write data to the memory device. The write commands targeting idle DIMMs are issued in sequence ahead of writes targeting busy DIMMs (or soon to be busy). Moving the data via a background write-to-buffer operation increases the efficiency of the common write data channel and allows the write data bus to reach maximum bandwidth during periods of heavy read activity. The actual write operations, deferred to periods of when the negative affects of the write can be completely/mostly hidden. In periods of light read activity or when there are no reads pending, buffering data in the memory module enables the buffered data to be written in parallel across multiple memory modules simultaneously.

摘要翻译： 内存模块设计有多个写入缓冲器，用于临时保存写入数据。 “写入缓冲”操作将内存控制器中的写入数据移动到写入缓冲区，同时内存模块正忙于处理读取操作。 然后，随后发出仅地址的“写入”命令来将缓冲的写入数据写入存储器件。 针对闲置DIMM的写命令在针对繁忙DIMM（或即将忙于）的写入之前按顺序发出。 通过后台写入缓冲操作移动数据可以提高通用写入数据通道的效率，并允许写入数据总线在重读操作期间达到最大带宽。 实际写入操作，延迟到写入负面影响的时期可以完全/大部分隐藏。 在光读取活动期间，或者当没有读取待处理时，缓冲存储器模块中的数据使缓冲数据能够同时跨多个存储器模块并行编写。

公开(公告)号：US20060179213A1

公开(公告)日：2006-08-10

申请号：US11054447

申请日：2005-02-09

申请人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

发明人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G06F13/1626

摘要： Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers while the memory module is busy processing read operations. Then, address-only “write” commands are later issued to write the buffered write data to the memory device. The write commands targeting idle DIMMs are issued in sequence ahead of writes targeting busy DIMMs (or soon to be busy). Moving the data via a background write-to-buffer operation increases the efficiency of the common write data channel and allows the write data bus to reach maximum bandwidth during periods of heavy read activity. The actual write operations, deferred to periods of when the negative affects of the write can be completely/mostly hidden. In periods of light read activity or when there are no reads pending, buffering data in the memory module enables the buffered data to be written in parallel across multiple memory modules simultaneously.

摘要翻译： 内存模块设计有多个写入缓冲器，用于临时保存写入数据。 “写入缓冲”操作将内存控制器中的写入数据移动到写入缓冲区，同时内存模块正忙于处理读取操作。 然后，随后发出仅地址的“写入”命令来将缓冲的写入数据写入存储器件。 针对闲置DIMM的写命令在针对繁忙DIMM（或即将忙于）的写入之前按顺序发出。 通过后台写入缓冲操作移动数据可以提高通用写入数据通道的效率，并允许写入数据总线在重读操作期间达到最大带宽。 实际写入操作，延迟到写入负面影响的时期可以完全/大部分隐藏。 在光读取活动期间，或者当没有读取待处理时，缓冲存储器模块中的数据使缓冲数据能够同时跨多个存储器模块并行编写。

公开(公告)号：US20060179206A1

公开(公告)日：2006-08-10

申请号：US11054066

申请日：2005-02-09

申请人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

发明人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

IPC分类号： G06F12/06

CPC分类号： G06F13/1647 ,  G11C5/04 ,  Y02D10/14

摘要： A set of N copies of bank control logic are provided for tracking the banks within the memory modules (DRAMS). When the total number of banks within the memory module(s) is greater than N, the addresses of particular banks are folded into a single grouping. The banks are represented by the N copies of the bank control logic even when the total number of banks is greater than N. Each bank within the group is tagged as being busy when any one of the banks in the group is the target of a memory access request. The algorithm folds the addresses of the banks in an order that substantially minimizes the likelihood that a bank that is in a busy or false busy state will be the target of another memory access request. Power and logic savings are recognized as only N copies of bank control logic have to be supported.

公开(公告)号：US20060179333A1

公开(公告)日：2006-08-10

申请号：US11054374

申请日：2005-02-09

申请人： Mark Brittain ,  Warren Maule

发明人： Mark Brittain ,  Warren Maule

IPC分类号： G11C5/00

CPC分类号： G11C11/4096 ,  G11C5/143 ,  G11C7/04 ,  G11C11/4074

摘要： A method and system for enabling directed temperature/power management at the DIMM-level and/or DRAM-level utilizing intelligent scheduling of memory access operations received at the memory controller. Hot spots within the memory subsystem, caused by operating the DIMMs/DRAMs above predetermined/preset threshold power/temperature values for operating a DIMM and/or a DRAM, are avoided/controlled by logic within the memory controller. The memory controller logic throttles the number/frequency at which commands (read/write operations) are issued to the specific DIMM/DRAM based on stored parameter values and tracking of outstanding operations issued to the memory subsystem devices.

摘要翻译： 一种用于利用在存储器控制器处接收的存储器访问操作的智能调度在DIMM级和/或DRAM级实现定向温度/电源管理的方法和系统。 由存储器控制器内的逻辑避免/控制存储器子系统内由于将DIMM / DRAM操作在高于用于操作DIMM和/或DRAM的预定阈值功率/温度值以上的DIMM / DRAM的热点。 存储器控制器逻辑基于存储的参数值和发出到存储器子系统设备的未完成操作的跟踪，来控制向特定DIMM / DRAM发出命令（读/写操作）的数量/频率。

公开(公告)号：US20080091906A1

公开(公告)日：2008-04-17

申请号：US11951752

申请日：2007-12-06

申请人： Mark Brittain ,  Edgar Cordero ,  Sanjeev Ghai ,  Warren Maule

发明人： Mark Brittain ,  Edgar Cordero ,  Sanjeev Ghai ,  Warren Maule

IPC分类号： G06F12/00

CPC分类号： A61C17/349 ,  A61C17/3436 ,  Y10T29/49826

摘要： A memory subsystem completes multiple read operations in parallel, utilizing the functionality of buffered memory modules in a daisy chain topology. A variable read latency is provided with each read command to enable memory modules to run independently in the memory subsystem. Busy periods of the memory device architecture are hidden by allowing data buses on multiple memory modules attached to the same data channel to run in parallel rather than in series and by issuing reads earlier than required to enable the memory devices to return from a busy state earlier. During scheduling of reads, the earliest received read whose target memory module is not busy is immediately issued at a next command cycle. The memory controller provides a delay parameter with each issued read. The number of cycles of delay is calculated to allow maximum utilization of the memory modules' data bus bandwidth without causing collisions on the memory channel.

摘要翻译： 存储器子系统并行完成多个读取操作，利用菊花链拓扑中的缓冲存储器模块的功能。 每个读取命令都提供了一个变量读取延迟，以使内存模块能够在存储器子系统中独立运行。 通过允许连接到同一数据通道的多个存储器模块上的数据总线并行运行而不是串行运行并且通过发出早于使存储器件从繁忙状态返回的所需的读数来隐藏存储器件架构的繁忙期 。 在读取调度期间，目标存储器模块不忙的最早接收到的读取将在下一个命令周期立即发出。 存储器控制器为每个发出的读取提供延迟参数。 计算延迟的周期数以允许最大限度地利用存储器模块的数据总线带宽而不引起存储器通道上的冲突。

公开(公告)号：US20060179262A1

公开(公告)日：2006-08-10

申请号：US11054446

申请日：2005-02-09

申请人： Mark Brittain ,  Edgar Cordero ,  Sanjeev Ghai ,  Warren Maule

发明人： Mark Brittain ,  Edgar Cordero ,  Sanjeev Ghai ,  Warren Maule

IPC分类号： G06F13/28

CPC分类号： G06F13/1631

摘要： A memory subsystem completes multiple read operations in parallel, utilizing the functionality of buffered memory modules in a daisy chain topology. A variable read latency is provided with each read command to enable memory modules to run independently in the memory subsystem. Busy periods of the memory device architecture are hidden by allowing data buses on multiple memory modules attached to the same data channel to run in parallel rather than in series and by issuing reads earlier than required to enable the memory devices to return from a busy state earlier. During scheduling of reads, the earliest received read whose target memory module is not busy is immediately issued at a next command cycle. The memory controller provides a delay parameter with each issued read. The number of cycles of delay is calculated to allow maximum utilization of the memory modules' data bus bandwidth without causing collisions on the memory channel.

摘要翻译： 存储器子系统并行完成多个读取操作，利用菊花链拓扑中的缓冲存储器模块的功能。 每个读取命令都提供了一个变量读取延迟，以使内存模块能够在存储器子系统中独立运行。 通过允许连接到同一数据通道的多个存储器模块上的数据总线并行运行而不是串行运行并且通过发出早于使存储器件从繁忙状态返回的读取的读取来隐藏存储器设备架构的繁忙周期 。 在读取调度期间，目标存储器模块不忙的最早接收到的读取将在下一个命令周期立即发出。 存储器控制器为每个发出的读取提供延迟参数。 计算延迟的周期数以允许最大限度地利用存储器模块的数据总线带宽而不引起存储器通道上的冲突。

公开(公告)号：US20060179362A1

公开(公告)日：2006-08-10

申请号：US11054417

申请日：2005-02-09

申请人： Luiz Alves ,  Mark Brittain ,  Timothy Dell ,  Sanjeev Ghai ,  Warren Maule ,  Scott Swaney

发明人： Luiz Alves ,  Mark Brittain ,  Timothy Dell ,  Sanjeev Ghai ,  Warren Maule ,  Scott Swaney

IPC分类号： G06F11/00

CPC分类号： G11C29/42 ,  G06F11/1044 ,  G11C5/04 ,  G11C29/4401 ,  G11C29/76 ,  G11C29/846 ,  G11C2029/0409

摘要： A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits 0:3) and a right half (for storing bits 4:7). A determination is made as to whether the data error was in the left or right half of the primary DRAM. The half of the primary DRAM in which the error occurred is removed from service. All subsequent reads and writes for data originally stored in the primary DRAM's defective half are made to a half of a spare DRAM in the DIMM, while the DRAM's non-defective half continues to be used for subsequently storing data.

摘要翻译： 提出了一种用于校正双列直插式存储器模块（DIMM）中的主动态随机存取存储器（DRAM）中的数据错误的方法和系统。 每个DRAM具有左半部分（用于存储位0：3）和右半部分（用于存储位4：7）。 确定数据错误是在主DRAM的左半还是右半部。 发生错误的主要DRAM的一半从服务中删除。 原始存储在主DRAM缺陷半部分的数据的所有后续读取和写入都被制成DIMM中的备用DRAM的一半，而DRAM的无缺陷半部分继续用于随后存储数据。

公开(公告)号：US20060179334A1

公开(公告)日：2006-08-10

申请号：US11054392

申请日：2005-02-09

申请人： Mark Brittain ,  Edgar Cordero ,  James Fields ,  Warren Maule ,  Eric Retter

发明人： Mark Brittain ,  Edgar Cordero ,  James Fields ,  Warren Maule ,  Eric Retter

IPC分类号： G06F1/32

CPC分类号： G06F1/3225 ,  G06F1/206 ,  Y02D10/16

摘要： A method and system for enabling directed temperature/power management at the DIMM-level and/or DRAM-level utilizing intelligent scheduling of memory access operations received at the memory controller. Hot spots within the memory subsystem, caused by operating the DIMMs/DRAMs above predetermined/preset threshold power/temperature values for operating a DIMM and/or a DRAM, are avoided/controlled by logic within the memory controller. The memory controller logic throttles the number/frequency at which commands (read/write operations) are issued to the specific DIMM/DRAM based on feedback data received from the specific DIMM/DRAM reaching the preset threshold power usage value.

摘要翻译： 一种用于利用在存储器控制器处接收的存储器访问操作的智能调度在DIMM级和/或DRAM级实现定向温度/电源管理的方法和系统。 由存储器控制器内的逻辑避免/控制存储器子系统内由于将DIMM / DRAM操作在用于操作DIMM和/或DRAM的预定/预设阈值功率/温度值以上的热点。 存储器控制器逻辑基于从特定DIMM / DRAM接收的反馈数据达到预设阈值功率使用值，来限制向特定DIMM / DRAM发出命令（读/写操作）的数量/频率。