公开(公告)号：US20200057942A1

公开(公告)日：2020-02-20

申请号：US16663876

申请日：2019-10-25

Applicant: Google LLC

Inventor： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC: G06N3/08 ,  G06N5/04 ,  G06N3/063 ,  G06F15/80

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

公开(公告)号：US20190354862A1

公开(公告)日：2019-11-21

申请号：US16529782

申请日：2019-08-01

Applicant: Google LLC

Inventor： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC: G06N3/08 ,  G06N5/04 ,  G06F15/80 ,  G06N3/063

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

公开(公告)号：US20190243645A1

公开(公告)日：2019-08-08

申请号：US16291176

申请日：2019-03-04

Applicant: Google LLC

Inventor： William Lacy ,  Gregory Michael Thorson ,  Christopher Aaron Clark ,  Norman Paul Jouppi ,  Thomas Norrie ,  Andrew Everett Phelps

IPC: G06F9/30 ,  G06F17/16 ,  G06F15/80 ,  G06F7/58 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F9/3001 ,  G06F7/588 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/3891 ,  G06F13/36 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/8046 ,  G06F15/8053 ,  G06F15/8092 ,  G06F17/16 ,  G06N3/063

Abstract: A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.

公开(公告)号：US20180285226A1

公开(公告)日：2018-10-04

申请号：US15875160

申请日：2018-01-19

Applicant: Google LLC

Inventor： Thomas Norrie ,  Naveen Kumar

IPC: G06F11/30 ,  G06F11/34 ,  G06F17/30 ,  G06F11/36 ,  G06F9/54

CPC classification number: G06F11/302 ,  G06F9/542 ,  G06F11/3072 ,  G06F11/3075 ,  G06F11/3476 ,  G06F11/3495 ,  G06F11/3636 ,  G06F17/30044 ,  G06F2201/86 ,  G06F2201/865

Abstract: A computer-implemented method executed by one or more processors, the method includes monitoring execution of program code executed by a first processor component; and monitoring execution of program code executed by a second processor component. A computing system stores data identifying hardware events in a memory buffer. The stored events occur across processor units that include at least the first and second processor components. The hardware events each include an event time stamp and metadata characterizing the event. The system generates a data structure identifying the hardware events. The data structure arranges the events in a time ordered sequence and associates events with at least the first or second processor components. The system stores the data structure in a memory bank of a host device and uses the data structure to analyze performance of the program code executed by the first or second processor components.