Machine with task-dependent control
    41.
    发明申请
    Machine with task-dependent control 有权
    机器与任务相关的控制

    公开(公告)号:US20090037072A1

    公开(公告)日:2009-02-05

    申请号:US11882234

    申请日:2007-07-31

    IPC分类号: G06G7/66

    CPC分类号: E02F9/2246 E02F9/2296

    摘要: A control system for a machine is disclosed. The control system may have a power source, an operator input device configured to generate a first signal indicative of a desired mode of power source operation, and a work implement driven by the power source. The control system may also have a controller in communication with the power source and the operator input device. The controller may be configured to classify a currently performed work implement task and select an output map based on the classification of the currently performed work implement task and the first signal. The controller may further be configured to control the power source operation using the output map.

    摘要翻译: 公开了一种用于机器的控制系统。 控制系统可以具有电源,被配置为产生指示期望的电源操作模式的第一信号的操作者输入装置和由电源驱动的工作装置。 控制系统还可以具有与电源和操作者输入装置通信的控制器。 控制器可以被配置为对当前执行的工作实现任务进行分类,并且基于当前执行的工作实现任务和第一信号的分类来选择输出映射。 控制器还可以被配置为使用输出图来控制电源操作。

    Machine status interlock for reversing fan control

    公开(公告)号:US20080136357A1

    公开(公告)日:2008-06-12

    申请号:US11634770

    申请日:2006-12-06

    IPC分类号: H02P1/00

    CPC分类号: F01P11/12

    摘要: The air circulation fan associated with a radiator of some machines may include an automatic reversing purge cycle that is utilized to dislodge material from the radiator and/or intake screen of the cooling system housing. The purge cycle is locked out when a person may be in the vicinity of the air intake screen of the machine. A controller determines that a person may be in the vicinity of the air intake screen when the machine is idle stationary, such as by determining that a parking brake is engaged. By locking out the purge cycle during machine idle stationary conditions, the risk of blowing dislodged dirt and/or debris onto a person, who may be servicing the machine or accessing an operator station, can be avoided.

    Complementary code keying demodulation system
    44.
    发明授权
    Complementary code keying demodulation system 失效
    互补码密钥解调系统

    公开(公告)号:US07079592B2

    公开(公告)日:2006-07-18

    申请号:US10170451

    申请日:2002-06-14

    IPC分类号: H04L27/22 H04L27/06 H04J11/00

    CPC分类号: H04L23/02

    摘要: The present invention relates to both of a bi-stage correlation calculation demodulation system, and a fast walsh block demodulation device at a receiver, wherein the bi-stage correlation calculation demodulation system has a characteristic of bi-stage correlation calculation in which the subsequent second-stage correlation calculations are dependent on the first-stage correlation calculation results by utilizing an incomplete orthogonal property within CCK codewords to arrange the CCK codewords operated in the first-stage correlation calculations and second-stage correlation calculations properly and respectively. The fast walsh block demodulation device comprises: a plurality of adders (operators) constructed to be a first-level correlation calculation circuit and a second-level correlation calculation circuit, and a plurality of process modules constructed to be a third-level correlation calculation circuit, the process modules having the functions of picking one maximum value from four values and performing third-level correlation calculation of conventional basic fast walsh block demodulation device.

    摘要翻译: 本发明涉及一种在接收机处的双级相关计算解调系统和快速沃尔什块解调装置,其中双级相关计算解调系统具有双级相关计算的特征,其中随后的第二 阶段相关计算依赖于第一阶段相关计算结果,通过利用CCK码字中的不完全正交特性来分别排列在第一阶段相关计算中运行的CCK码字和二阶相关计算。 快速沃尔什块解调装置包括:构成为第一级相关计算电路和第二级相关计算电路的多个加法器(运算符),以及构成为第三级相关计算电路的多个处理模块 该处理模块具有从四个值中选出一个最大值并执行常规基本快速沃尔什块解调装置的第三级相关计算的功能。

    Charge pump circuit without body effects

    公开(公告)号:US06642773B2

    公开(公告)日:2003-11-04

    申请号:US10064714

    申请日:2002-08-09

    IPC分类号: G05F110

    摘要: A charge pump circuit has input and output nodes, a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. A drain of the first transistor and a drain of the second transistor are connected to the input node. A source of the second transistor and a drain of the third transistor are connected to the output node. The first capacitor is connected to a gate of the second transistor. The third transistor is connected to a substrate and a source of the second transistor. When the first transistor is turned on, a voltage at the input node will charge the first capacitor. When the second transistor is turned on, the third transistor is turned on simultaneously so that the substrate and the source of the second transistor will reach the same voltage level. Then, voltage at the input node will charge the second capacitor.