公开(公告)号：US20180323100A1

公开(公告)日：2018-11-08

申请号：US15772711

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Paul A. NYHUS ,  Mohit K. HARAN ,  Charles H. WALLACE ,  Robert M. BIGWOOD ,  Deepak S. RAO ,  Alexander F. KAPLAN

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76877 ,  H01L21/76897

Abstract: Via CD control for BEOL interconnects is described. For example, a method of fabricating an interconnect structure includes forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate. The method also includes forming an inter-layer dielectric layer above the metallization layer. The method also includes forming a first grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. The method also includes forming a second grating pattern above the first grating pattern. The method also includes patterning the inter-layer dielectric layer using the first grating pattern and the second grating pattern to form via locations and line regions in the inter-layer dielectric layer. The method also includes forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.