公开(公告)号：US20190206728A1

公开(公告)日：2019-07-04

申请号：US16329172

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Charles H. WALLACE ,  Marvin Y. PAIK ,  Hyunsoo PARK ,  Mohit K. HARAN ,  Alexander F. KAPLAN ,  Ruth A. BRAIN

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528

Abstract: Methods and architectures for IC interconnect trenches, and trench plugs that define separations between two adjacent trench ends. Plugs and trenches may be defined through a multiple patterning process. An upper grating pattern may be summed with a plug keep pattern into a pattern accumulation layer. The pattern accumulation layer may be employed to define plug masks. A lower grating pattern may then be summed with the plug masks to define a pattern in trench ILD material, which can then be backfilled with interconnect metallization. As such, a complex damascene interconnect structure can be fabricated at the scaled-down geometries achievable with pitch-splitting techniques. In some embodiments, the trenches are located at spaces between first spacer masks defined in a patterning process associated with the first grating pattern while the plug masks are located based on a tone-inversion of second spacer masks associated with the second grating pattern.

公开(公告)号：US20190259656A1

公开(公告)日：2019-08-22

申请号：US16402664

申请日：2019-05-03

Applicant: Intel Corporation

Inventor： Paul A. NYHUS ,  Mohit K. HARAN ,  Charles H. WALLACE ,  Robert M. BIGWOOD ,  Deepak S. RAO ,  Alexander F. KAPLAN

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311

Abstract: Via CD control for BEOL interconnects is described. For example, a method of fabricating an interconnect structure includes forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate. The method also includes forming an inter-layer dielectric layer above the metallization layer. The method also includes forming a first grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. The method also includes forming a second grating pattern above the first grating pattern. The method also includes patterning the inter-layer dielectric layer using the first grating pattern and the second grating pattern to form via locations and line regions in the inter-layer dielectric layer. The method also includes forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.

公开(公告)号：US20220068707A1

公开(公告)日：2022-03-03

申请号：US17521753

申请日：2021-11-08

Applicant: Intel Corporation

Inventor： Charles H. WALLACE ,  Marvin Y. PAIK ,  Hyunsoo PARK ,  Mohit K. HARAN ,  Alexander F. KAPLAN ,  Ruth A. BRAIN

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: Methods and architectures for IC interconnect trenches, and trench plugs that define separations between two adjacent trench ends. Plugs and trenches may be defined through a multiple patterning process. An upper grating pattern may be summed with a plug keep pattern into a pattern accumulation layer. The pattern accumulation layer may be employed to define plug masks. A lower grating pattern may then be summed with the plug masks to define a pattern in a trench ILD material, which can then be backfilled with interconnect metallization. As such, a complex damascene interconnect structure can be fabricated at the scaled-down geometries achievable with pitch-splitting techniques. In some embodiments, the trenches are located at spaces between first spacer masks defined in a patterning process associated with the first grating pattern while the plug masks are located based on a tone-inversion of second spacer masks associated with the second grating pattern.

公开(公告)号：US20180323100A1

公开(公告)日：2018-11-08

申请号：US15772711

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Paul A. NYHUS ,  Mohit K. HARAN ,  Charles H. WALLACE ,  Robert M. BIGWOOD ,  Deepak S. RAO ,  Alexander F. KAPLAN

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76877 ,  H01L21/76897

Abstract: Via CD control for BEOL interconnects is described. For example, a method of fabricating an interconnect structure includes forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate. The method also includes forming an inter-layer dielectric layer above the metallization layer. The method also includes forming a first grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. The method also includes forming a second grating pattern above the first grating pattern. The method also includes patterning the inter-layer dielectric layer using the first grating pattern and the second grating pattern to form via locations and line regions in the inter-layer dielectric layer. The method also includes forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.