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公开(公告)号：US10833868B2
公开(公告)日：2020-11-10
申请号：US15856179
申请日：2017-12-28
Applicant: Intel Corporation
Inventor： Andrew Reinders , Manoj Sastry , Santosh Ghosh , Rafael Misoczki
Abstract: A technique includes generating a direct anonymous attestation (DAA)-based signature to prove an electronic device is a member of a group. Generating the signature includes determining a reciprocal of a prime modulus, and determining the reciprocal of the prime modulus comprises left bit shifting a Barrett multiplier by a predetermined number of bits and multiplying a result of the left bit shifting of the Barrett multiplier with the prime modulus.
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公开(公告)号：US20200320206A1
公开(公告)日：2020-10-08
申请号：US16910958
申请日：2020-06-24
Applicant: Intel Corporation
Inventor： Rosario Cammarota , Fabian Boemer , Casimir M. Wierzynski , Anand Rajan , Rafael Misoczki
Abstract: Systems, methods, apparatus, and articles of manufacture to prevent unauthorized release of information associated with a function as a service are disclosed. A system disclosed herein operates on in-use information. The system includes a function as a service of a service provider that operates on encrypted data. The encrypted data includes encrypted in-use data. The system also includes a trusted execution environment (TEE) to operate within a cloud-based environment of a cloud provider. The function as a service operates on the encrypted data within the TEE, and the TEE protects service provider information from access by the cloud provider. The encrypted in-use data and the service provider information form at least a portion of the in-use information.
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公开(公告)号：US10715335B2
公开(公告)日：2020-07-14
申请号：US16026657
申请日：2018-07-03
Applicant: Intel Corporation
Inventor： Steffen Schulz , Rafael Misoczki , Manoj R. Sastry , Jesse Walker
Abstract: In a method for validating software updates, a data processing system contains a current version of a software component. The data processing system saves at least first and second current advance keys (AKs). After saving the current AKs, the data processing system receives an update package for a new version of the software component. The data processing system extracts a digital signature and two or more new AKs from the update package. The data processing system uses at least one current AK to determine whether the digital signature is valid. In response to a determination that the digital signature is valid, the data processing system uses a software image from the update package to update the software component, and the data processing system saves the new AKs, for subsequent utilization as the current AKs.
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公开(公告)号：US20190325166A1
公开(公告)日：2019-10-24
申请号：US16456339
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Vikram Suresh , Sanu Mathew , Rafael Misoczki , Santosh Ghosh , Raghavan Kumar , Manoj Sastry , Andrew H. Reinders
Abstract: Embodiments are directed to post quantum public key signature operation for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including a dedicated cryptographic hash hardware engine, and a reconfigurable fabric including logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device for public key signature operation, including mapping a state machine for public key generation and verification to the reconfigurable fabric, including mapping one or more cryptographic hash engines to the reconfigurable fabric, and combining the dedicated cryptographic hash hardware engine with the one or more mapped cryptographic hash engines for cryptographic signature generation and verification.
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公开(公告)号：US20190319787A1
公开(公告)日：2019-10-17
申请号：US16456096
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： ANDREW H. REINDERS , Santosh Ghosh , Manoj Sastry , Rafael Misoczki
Abstract: In one example an apparatus comprises an unsatisfied parity check (UPC) memory, an unsatisfied parity check (UPC) compute block communicatively coupled to the UPC memory, a first error memory communicatively coupled to the UPC compute block, a polynomial multiplication syndrome memory, a polynomial multiplication compute block communicatively coupled to the polynomial multiplication syndrome memory, a second error memory communicatively coupled to the polynomial multiplication compute block, a codeword memory communicatively coupled to the UPC compute block and the polynomial multiplication compute block, a multiplexer communicatively coupled to first error memory and to the polynomial multiplication compute block, and a controller communicatively coupled to the UPC memory, the polynomial multiplication syndrome memory, the codeword memory, and the multiplexer. Other examples may be described.
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Patent Agency Ranking
公开(公告)号：US20190319782A1
公开(公告)日：2019-10-17
申请号：US16455950
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： SANTOSH GHOSH , Vikram Suresh , Sanu Mathew , Manoj Sastry , Andrew H. Reinders , Raghavan Kumar , Rafael Misoczki
Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.
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公开(公告)号：US10404468B2
公开(公告)日：2019-09-03
申请号：US15351606
申请日：2016-11-15
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Manoj R. Sastry , Jesse Walker , Li Zhao , Rafael Misoczki
Abstract: Technologies for counter with CBC-MAC (CCM) mode encryption include a computing device that performs a CBC-MAC authentication operation on a message with an encryption key, using a 64-bit block cipher to generate a message authentication code. The computing device generates a first 64-bit authentication block including an 8-bit flag field and a length field of between 11 and 32 bits. The flag field indicates the length of the length field. Performing the CBC-MAC authentication operation includes formatting the message into one or more 64-bit authentication blocks. The computing device performs a counter mode encryption operation on the message with the encryption key using the 64-bit block cipher to generate a cipher text. Performing the counter mode encryption includes generating multiple 64-bit keystream blocks. The computing device generates an authentication tag based on the message authentication code and a first keystream block of keystream blocks. Other embodiments are described and claimed.
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公开(公告)号：US20180091309A1
公开(公告)日：2018-03-29
申请号：US15277462
申请日：2016-09-27
Applicant: Intel Corporation
Inventor： Rafael Misoczki , Steffen Schulz , Manoj R. Sastry , Santosh Ghosh , Li Zhao
IPC: H04L9/32
CPC classification number: H04L9/3247 , H04L9/3242 , H04L9/3252 , H04L2209/30 , H04L2209/38
Abstract: One embodiment provides a signer device. The signer device includes hash signature control logic and signer signature logic. The hash signature control logic is to retrieve a first nonce, to concatenate the first nonce and a message to be transmitted and to determine whether a first message representative satisfies a target threshold. The signer signature logic is to generate a first transmitted signature based, at least in part, on the first message representative, if the first message representative satisfies the target threshold. The hash signature control logic is to retrieve a second nonce, concatenate the second nonce and the message to be transmitted and to determine whether a second message representative satisfies the target threshold, if the first message representative does not satisfy the target threshold.
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公开(公告)号：US11792191B2
公开(公告)日：2023-10-17
申请号：US17650767
申请日：2022-02-11
Applicant: Intel Corporation
Inventor： Xiruo Liu , Rafael Misoczki , Santosh Ghosh , Manoj Sastry
CPC classification number: H04L63/0869 , H04L9/0852 , H04L9/3242 , H04L9/3265
Abstract: In one example a prover device comprises one or more processors, a computer-readable memory, and signature logic to store a first cryptographic representation of a first trust relationship between the prover device and a verifier device, the first cryptographic representation based on a pair of asymmetric hash-based multi-time signature keys, receive an attestation request message from the verifier device, the attestation request message comprising attestation data for the verifier device and a hash-based signature generated by the verifier device, and in response to the attestation request message, to verify the attestation data, verify the hash-based signature generated by the verifier device using a public key associated with the verifier device, generate an attestation reply message using a hash-based multi-time private signature key and send the attestation reply message to the verifier device. Other examples may be described.
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公开(公告)号：US11575521B2
公开(公告)日：2023-02-07
申请号：US16455967
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Rafael Misoczki , Vikram Suresh , David Wheeler , Santosh Ghosh , Manoj Sastry
Abstract: In one example an apparatus comprises accelerator logic to pre-compute at least a portion of a message representative, hash logic to generate the message representative based on an input message, and signature logic to generate a signature to be transmitted in association with the message representative, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and determine whether the message representative satisfies a target threshold allocation of computational costs between a cost to generate the signature and a cost to verify the signature. Other examples may be described.
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