公开(公告)号：US10037210B2

公开(公告)日：2018-07-31

申请号：US15257833

申请日：2016-09-06

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Erdinc Ozturk ,  Vinodh Gopal ,  Wajdi K. Feghali ,  Sean M. Gulley ,  Martin G. Dixon

IPC: G06F7/57 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F7/525 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3893

Abstract: An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register.

公开(公告)号：US09658854B2

公开(公告)日：2017-05-23

申请号：US14498931

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Sean M. Gulley ,  Kirk S. Yap ,  Wajdi K. Feghali

IPC: G06F21/60 ,  G06F9/30 ,  G06F21/72

CPC classification number: G06F9/30145 ,  G06F9/30007 ,  G06F9/30036 ,  G06F21/72

Abstract: Instructions and logic provide SIMD SM3 cryptographic hashing functionality. Some embodiments include a processor comprising: a decoder to decode instructions for a SIMD SM3 message expansion, specifying first and second source data operand sets, and an expansion extent. Processor execution units, responsive to the instruction, perform a number of SM3 message expansions, from the first and second source data operand sets, determined by the specified expansion extent and store the result into a SIMD destination register. Some embodiments also execute instructions for a SIMD SM3 hash round-slice portion of the hashing algorithm, from an intermediate hash value input, a source data set, and a round constant set. Processor execution units perform a set of SM3 hashing round iterations upon the source data set, applying the intermediate hash value input and the round constant set, and store a new hash value result in a SIMD destination register.

公开(公告)号：US20170033928A1

公开(公告)日：2017-02-02

申请号：US15289819

申请日：2016-10-10

Applicant: Intel Corporation

Inventor： Sean M. Gulley ,  Gilbert M. Wolrich, IV ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

IPC: H04L9/08 ,  G06F9/38 ,  H04L9/06

CPC classification number: H04L9/0869 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/3895 ,  G06F21/72 ,  G09C1/00 ,  H04L9/0618 ,  H04L2209/12 ,  H04L2209/24

Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

Abstract translation: 指令和逻辑提供单指令多数据（SIMD）SM4圆切片操作。 指令的实施例指定第一和第二源数据操作数集合，以及替换功能指示符，例如， 在一个立即操作数。 处理器的实施例可以包括响应于第一指令的加密单元，以在第一源数据操作数集合的一部分上执行与来自第二源数据操作数集合的对应密钥的一组SM4-圆交换，以响应于 替代功能指示符，其指示第一替换功能，响应于指示第二替代函数的替换函数指示符，使用来自第二源数据操作数集合的相应常数的第一源数据操作数集合的另一部分执行SM4密钥生成片段 并将第一指令的一组结果元素存储在SIMD目的地寄存器中。

公开(公告)号：US09467279B2

公开(公告)日：2016-10-11

申请号：US14498633

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Sean M. Gulley ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

IPC: H04L9/06 ,  G06F21/72 ,  G06F9/30 ,  G09C1/00 ,  H04L9/08

CPC classification number: H04L9/0869 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/3895 ,  G06F21/72 ,  G09C1/00 ,  H04L9/0618 ,  H04L2209/12 ,  H04L2209/24

Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

Abstract translation: 指令和逻辑提供单指令多数据（SIMD）SM4圆切片操作。 指令的实施例指定第一和第二源数据操作数集合，以及替换功能指示符，例如， 在一个立即操作数。 处理器的实施例可以包括响应于第一指令的加密单元，以在第一源数据操作数集合的一部分上执行与来自第二源数据操作数集合的对应密钥的一组SM4-圆交换，以响应于 替代功能指示符，其指示第一替换功能，响应于指示第二替代函数的替代函数指示符，使用来自第二源数据操作数集合的相应常数的第一源数据操作数集合的另一部分来执行SM4密钥生成片段 并将第一指令的一组结果元素存储在SIMD目的地寄存器中。

公开(公告)号：US20160094340A1

公开(公告)日：2016-03-31

申请号：US14498633

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Sean M. Gulley ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

IPC: H04L9/06 ,  G06F21/72 ,  G06F9/30 ,  H04L9/08

CPC classification number: H04L9/0869 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/3895 ,  G06F21/72 ,  G09C1/00 ,  H04L9/0618 ,  H04L2209/12 ,  H04L2209/24

Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

Abstract translation: 指令和逻辑提供单指令多数据（SIMD）SM4圆切片操作。 指令的实施例指定第一和第二源数据操作数集合，以及替换功能指示符，例如， 在一个立即操作数。 处理器的实施例可以包括响应于第一指令的加密单元，以在第一源数据操作数集合的一部分上执行与来自第二源数据操作数集合的对应密钥的一组SM4-圆交换，以响应于 替代功能指示符，其指示第一替换功能，响应于指示第二替代函数的替代函数指示符，使用来自第二源数据操作数集合的相应常数的第一源数据操作数集合的另一部分来执行SM4密钥生成片段 并将第一指令的一组结果元素存储在SIMD目的地寄存器中。

公开(公告)号：US20140205084A1

公开(公告)日：2014-07-24

申请号：US13995457

申请日：2011-12-22

Applicant: INTEL CORPORATION

Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  Vinodh Gopal ,  James D. Guilford ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC: H04L9/14 ,  G06F21/60

CPC classification number: H04L9/14 ,  G06F9/30007 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3893 ,  G06F21/602 ,  H04L9/3239

Abstract: A method is described. The method includes executing one or more JH_SBOX_L instructions to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_P instructions to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed.

Abstract translation: 描述了一种方法。 该方法包括执行一个或多个JH_SBOX_L指令以在JH状态上执行S-Box映射和线性（L）变换，并且一旦S-Box映射和 L变换。

公开(公告)号：US20140164467A1

公开(公告)日：2014-06-12

申请号：US13996529

申请日：2011-12-23

Applicant: INTEL CORPORATION

Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Erdinc Ozturk ,  Vinodh Gopal ,  Wajdi K. Feghali ,  Sean M. Gulley ,  Martin G. Dixon

IPC: G06F7/57

CPC classification number: G06F9/3016 ,  G06F7/525 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3893

Abstract: An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register.

Abstract translation: 描述了一种装置，其包括具有指令执行流水线的半导体芯片，该指令执行流水线具有一个或多个具有相应逻辑电路的执行单元，以便：a）执行将第一输入操作数和第二输入操作数相乘并且呈现下一部分的第一指令 其中，第一和第二输入操作数是第一和第二输入向量的相应元素; b）执行第二指令，其将第一输入操作数和第二输入操作数相乘并呈现结果的上部，其中第一和第二输入操作数是第一和第二输入向量的相应元素; 以及c）执行加法指令，其中加法指令的相加的进位项被记录在掩码寄存器中。