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    Apparatuses, methods, and systems for blockchain transaction acceleration
    1.
    发明授权
    Apparatuses, methods, and systems for blockchain transaction acceleration 有权

    公开(公告)号：US10761877B2

    公开(公告)日：2020-09-01

    申请号：US15884259

    申请日：2018-01-30

    申请人： Intel Corporation

    发明人： Simon N. Peffers ,  Sean M. Gulley

    IPC分类号： G06F9/46 ,  G06F9/50 ,  H04L9/08 ,  H04L9/30 ,  H04L9/32

    摘要： Methods and apparatuses relating to accelerating blockchain transactions are described. In one embodiment, a processor includes a hardware accelerator to execute an operation of a blockchain transaction, and the hardware accelerator includes a dispatcher circuit to route the operation to a transaction processing circuit when the operation is a transaction operation and route the operation to a block processing circuit when the operation is a block operation. In another embodiment, a processor includes a hardware accelerator to execute an operation of a blockchain transaction; and a network interface controller including a dispatcher circuit to route the operation to a transaction processing circuit of the hardware accelerator when the operation is a transaction operation and route the operation to a block processing circuit of the hardware accelerator when the operation is a block operation.

    Memory controller and methods for memory compression utilizing a hardware compression engine and a dictionary to indicate a zero value, full match, partial match, or no match
    3.
    发明授权
    Memory controller and methods for memory compression utilizing a hardware compression engine and a dictionary to indicate a zero value, full match, partial match, or no match 有权

    公开(公告)号：US10509580B2

    公开(公告)日：2019-12-17

    申请号：US15089456

    申请日：2016-04-01

    申请人： Intel Corporation

    发明人： Kirk S. Yap ,  Vinodh Gopal ,  James D. Guilford ,  Sean M. Gulley

    IPC分类号： G06F3/06 ,  G06F12/00 ,  H03M7/30

    摘要： Methods and apparatuses relating to memory compression and decompression are described, including a memory controller and methods for memory compression utilizing a hardware compression engine and a dictionary to indicate a zero value, full match, partial match, or no match. When indices for multiple sections are the same, an entry in the dictionary may be updated with the value of the section that is most recent, in the same order as in the block of data. In one embodiment, a hardware compression engine is to determine when each section of a plurality of sections of a block of data is a zero value, a full match or a partial match to an entry in a dictionary, or a no match to any entry in the dictionary, encode a tag for each section to indicate the one of the zero value, the full match, the partial match, and the no match, encode a literal when the section is the no match, an index to the entry in the dictionary when the section is the full match, and an index to the entry in the dictionary and non-matching bits when the section is the partial match, and update an entry in the dictionary with a value of a section when the section is the no match, wherein tags for the plurality of sections are to be output from the hardware compression engine in a single field, literals for the plurality of sections are to be output from the hardware compression engine in a single field, indexes for the plurality of sections are to be output from the hardware compression engine in a single field, and non-matching bits for the plurality of sections are to be output from the hardware compression engine in a single field. A hash value may be generated for each of a plurality of sections of a block of data to use as an index in a dictionary.

    Systems, methods, and apparatuses for decompression using hardware and software
    9.
    发明授权
    Systems, methods, and apparatuses for decompression using hardware and software 有权

    公开(公告)号：US10069512B2

    公开(公告)日：2018-09-04

    申请号：US15479087

    申请日：2017-04-04

    申请人： Intel Corporation

    发明人： Vinodh Gopal ,  James D. Guilford ,  Kirk S. Yap ,  Sean M. Gulley ,  Gilbert M. Wolrich

    IPC分类号： H03M7/30 ,  H03M7/46

    摘要： Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. For example, in embodiment a hardware apparatus comprises an input buffer to store incoming data from a compressed stream, a selector to select at least one byte stored in the input buffer, a decoder to decode the selected at least one byte and determine if the decoded at least one byte is a literal or a symbol, an overlap condition, a size of a record from the decoded stream, a length value of the data to be retrieved from the decoded stream, and an offset value for the decoded data, and a token format converter to convert the decoded data and data from source and destination offset base registers into a fixed-length token.