公开(公告)号：US11531542B2

公开(公告)日：2022-12-20

申请号：US17393361

申请日：2021-08-03

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Matthew C. Merten ,  Tong Li ,  Bret L. Toll

IPC: G06F9/30 ,  G06F9/38

Abstract: A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

公开(公告)号：US10725779B2

公开(公告)日：2020-07-28

申请号：US16450319

申请日：2019-06-24

Applicant: Intel Corporation

Inventor： Kirk S. Yap ,  Gilbert M. Wolrich ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC: G06F9/30 ,  G06F21/60 ,  G06F12/0875 ,  G06F12/1027 ,  G09C1/00 ,  H04L9/32 ,  G06F9/38 ,  G06F12/0897 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42 ,  G06F15/80 ,  H04L9/06

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US09495165B2

公开(公告)日：2016-11-15

申请号：US14556931

申请日：2014-12-01

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Erdinc Ozturk ,  Wajdi K. Feghali ,  Gilbert M. Wolrich ,  Martin G. Dixon

IPC: G06F7/00 ,  G06F7/38 ,  G06F1/02 ,  G06F17/50 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3893

Abstract: Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.

公开(公告)号：US20150089201A1

公开(公告)日：2015-03-26

申请号：US14562310

申请日：2014-12-05

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean Mirkes ,  Bret L. Toll ,  Maxim Loktyukhin ,  Mark C. Davis ,  Alexandre J. Farcy

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30094 ,  G06F9/30098

Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

Abstract translation: 一个方面的方法可以包括接收旋转指令。 旋转指令可以指示源操作数和旋转量。 结果可以存储在由旋转指令指示的目标操作数中。 结果可能使源操作数旋转了旋转量。 旋转指令的执行可以在不读取进位标志的情况下完成。

公开(公告)号：US20220027154A1

公开(公告)日：2022-01-27

申请号：US17496632

申请日：2021-10-07

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Matthew C. Merten ,  Tong Li ,  Bret T. Toll, I

IPC: G06F9/30 ,  G06F9/38

Abstract: A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

公开(公告)号：US10684855B2

公开(公告)日：2020-06-16

申请号：US15686889

申请日：2017-08-25

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Erdinc Ozturk ,  Wajdi K. Feghali ,  Gilbert M. Wolrich ,  Martin G. Dixon

IPC: G06F7/00 ,  G06F7/38 ,  G06F1/02 ,  G06F17/50 ,  G06F9/30 ,  G06F9/38

Abstract: Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.

公开(公告)号：US20180157489A1

公开(公告)日：2018-06-07

申请号：US15716258

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Kirk S. Yap ,  Gilbert M. Wolrich ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC: G06F9/30 ,  H04L9/06

CPC classification number: G06F9/30145 ,  H04L9/0643 ,  H04L2209/122

Abstract: A processor includes a plurality of registers, an instruction decoder to receive an instruction to process a KECCAK state cube of data representing a KECCAK state of a KECCAK hash algorithm, to partition the KECCAK state cube into a plurality of subcubes, and to store the subcubes in the plurality of registers, respectively, and an execution unit coupled to the instruction decoder to perform the KECCAK hash algorithm on the plurality of subcubes respectively stored in the plurality of registers in a vector manner.

公开(公告)号：US09940130B2

公开(公告)日：2018-04-10

申请号：US14562223

申请日：2014-12-05

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D Guilford ,  Gilbert M Wolrich ,  Wajdi K Feghali ,  Erdinc Ozturk ,  Martin G Dixon ,  Sean Mirkes ,  Bret L Toll ,  Maxim Loktyukhin ,  Mark C Davis ,  Alexandre J Farcy

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30094 ,  G06F9/30098

Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

公开(公告)号：US09916160B2

公开(公告)日：2018-03-13

申请号：US14562145

申请日：2014-12-05

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K Feghali ,  Erdinc Ozturk ,  Martin G Dixon ,  Sean Mirkes ,  Bret L Toll ,  Maxim Loktyukhin ,  Mark C Davis ,  Alexandre J Farcy

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30094 ,  G06F9/30098

Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

公开(公告)号：US09900770B2

公开(公告)日：2018-02-20

申请号：US15238698

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Erdinc Ozturk ,  Kirk S. Yap ,  Wajdi K. Feghali

IPC: G06F15/00 ,  G06F7/00 ,  H04W12/02 ,  G09C1/00 ,  H04L9/06 ,  G06F9/30 ,  G06F9/38 ,  H04W12/04 ,  H04L29/06

CPC classification number: H04W12/02 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30134 ,  G06F9/3887 ,  G09C1/00 ,  H04L9/065 ,  H04L9/0668 ,  H04L63/045 ,  H04L63/0457 ,  H04W12/04

Abstract: Vector instructions for performing SNOW 3G wireless security operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first operand of the first instruction specifying a first vector register that stores a current state of a finite state machine (FSM). The execution circuitry also receives a second operand of the first instruction specifying a second vector register that stores data elements of a liner feedback shift register (LFSR) that are needed for updating the FSM. The execution circuitry executes the first instruction to produce a updated state of the FSM and an output of the FSM in a destination operand of the first instruction.