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    Instructions processors, methods, and systems to process secure hash algorithms
    2.
    发明授权
    Instructions processors, methods, and systems to process secure hash algorithms 有权

    公开(公告)号：US10911222B2

    公开(公告)日：2021-02-02

    申请号：US16807021

    申请日：2020-03-02

    Applicant: Intel Corporation

    Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  Vinodh Gopal ,  James D. Guilford

    IPC: H04L9/06 ,  G06F21/64 ,  G06F9/30 ,  G06F21/72 ,  G06F21/60

    Abstract: A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.

    Secure modular exponentiation processors, methods, systems, and instructions
    5.
    发明授权
    Secure modular exponentiation processors, methods, systems, and instructions 有权

    公开(公告)号：US10089500B2

    公开(公告)日：2018-10-02

    申请号：US14866334

    申请日：2015-09-25

    Applicant: INTEL CORPORATION

    Inventor： Vinodh Gopal ,  Gilbert M. Wolrich

    IPC: H04L29/00 ,  G06F21/72 ,  G06F9/30 ,  H04L9/08

    Abstract: A processor of an aspect includes a decode unit to decode a modular exponentiation with obfuscated input information instruction. The modular exponentiation with obfuscated input information instruction is to indicate a plurality of source operands that are to store input information for a modular exponentiation operation. At least some of the input information that is to be stored in the plurality of source operands is to be obfuscated. An execution unit is coupled with the decode unit. The execution unit, in response to the modular exponentiation with obfuscated input information instruction, is to store a modular exponentiation result in a destination storage location that is to be indicated by the modular exponentiation with obfuscated input information instruction. Other processors, methods, systems, and instructions are disclosed.

    HETEROGENEOUS COMPRESSION ARCHITECTURE FOR OPTIMIZED COMPRESSION RATIO
    6.
    发明申请
    HETEROGENEOUS COMPRESSION ARCHITECTURE FOR OPTIMIZED COMPRESSION RATIO 有权

    公开(公告)号：US20170111059A1

    公开(公告)日：2017-04-20

    申请号：US15393599

    申请日：2016-12-29

    Applicant: Intel Corporation

    Inventor： James D. Guilford ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel F. Cutter

    IPC: H03M7/40 ,  H03M7/30

    CPC classification number: H03M7/40 ,  H03M7/30 ,  H03M7/3086

    Abstract: A processing device includes an accelerator circuit to identify a byte in a byte stream, determine whether a first byte string starting from a first byte position of the byte matches a second byte string starting from a second byte position, responsive to determining that the first byte string matches the second byte string, generate a token comprising a first symbol encoding a length of the first byte string and a second symbol encoding a byte distance between the first byte position and the second byte position, and responsive to determining that the first byte string does not match another byte string, generate the token comprising the first symbol comprising the byte and a second symbol encoding a determined value.

    Heterogeneous compression architecture for optimized compression ratio
    8.
    发明授权
    Heterogeneous compression architecture for optimized compression ratio 有权
    用于优化压缩比的异构压缩架构

    公开(公告)号：US09537504B1

    公开(公告)日：2017-01-03

    申请号：US14866115

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： James D. Guilford ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel F. Cutter

    IPC: H03M7/30 ,  H03M7/40

    CPC classification number: H03M7/40 ,  H03M7/30 ,  H03M7/3086

    Abstract: A processing device includes a storage device to store data and a processor, operably coupled to the storage device, the processor to receive a token stream comprising a plurality of tokens generated based on a byte stream comprising a plurality of bytes, wherein each token in the token stream comprises at least one symbol associated with a respective byte in the byte stream, and wherein the at least one symbol represents one of the respective byte, a length of a first byte string starting from the respective byte, or a byte distance between the first byte string and a matching second byte string, generate a graph comprising a plurality of nodes and edges based on the token stream, wherein each token in the token stream is associated with a respective node connected by at least one edge to another node, and wherein the at least one edge is associated with a cost function to encode the at least one symbol stored in the each token, identify, based on the graph, a path between a first node associated with a beginning token of the token stream and an end node associated with a last token of the token stream, wherein the path comprises a subset of nodes and edges linking the subset of nodes, and perform variable-length encoding of a subset of tokens associated with the subset of nodes to generate an output data.

    Abstract translation: 处理设备包括存储数据的存储设备和可操作地耦合到存储设备的处理器，处理器接收包括基于包括多个字节的字节流生成的多个令牌的令牌流，其中， 标记流包括与字节流中的相应字节相关联的至少一个符号，并且其中至少一个符号表示相应字节中的一个，从相应字节开始的第一字节串的长度，或 第一字节串和匹配的第二字节串，基于令牌流生成包括多个节点和边的图形，其中令牌流中的每个令牌与由至少一个边缘连接到另一个节点的相应节点相关联，以及 其中所述至少一个边缘与成本函数相关联，以对存储在每个令牌中的所述至少一个符号进行编码，基于所述图表来识别第一点之间的路径 e与令牌流的开始令牌和与令牌流的最后一个令牌相关联的结束节点相关联，其中该路径包括链接节点子集的节点和边缘的子集，并且执行子集的子集的可变长度编码 与节点子集相关联的令牌以生成输出数据。

    APPARATUS AND METHOD TO ACCELERATE COMPRESSION AND DECOMPRESSION OPERATIONS
    10.
    发明申请
    APPARATUS AND METHOD TO ACCELERATE COMPRESSION AND DECOMPRESSION OPERATIONS 有权
    装置和方法来加速压缩和分解操作

    公开(公告)号：US20150256195A1

    公开(公告)日：2015-09-10

    申请号：US14595129

    申请日：2015-01-12

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich

    IPC: H03M7/30

    CPC classification number: H03M7/3086 ,  G06F9/30145 ,  G06F9/30178

    Abstract: Methods and apparatuses relating to an instruction to decode encoded information of a compression scheme are described. In one embodiment, a processor includes a decode unit to decode an instruction, and an execution unit to execute the instruction, the execution unit including a state machine and content addressable memory (CAM) circuitry, the state machine to receive a pointer to a stream of encoded information of a compression scheme, fetch a section of the encoded information, and apply the section of the encoded information to the CAM circuitry to obtain decoded information.

    Abstract translation: 描述与解码压缩方案的编码信息的指令相关的方法和装置。 在一个实施例中，处理器包括解码指令的解码单元和执行指令的执行单元，执行单元包括状态机和内容可寻址存储器（CAM）电路，状态机接收指向流的指针 的压缩方案的编码信息，获取编码信息的一部分，并将编码信息的部分应用于CAM电路以获得解码信息。

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