公开(公告)号：US10200310B2

公开(公告)日：2019-02-05

申请号：US14757892

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： James Dinan ,  Mario Flajslik ,  Keith Underwood ,  David Keppel ,  Ulf Rainer Hanebutte

IPC: G06F15/167 ,  H04L12/931 ,  G06F15/173

Abstract: In an example, there is disclosed a compute node, comprising: first one or more logic elements comprising a data producer engine to produce a datum; and a host fabric interface to communicatively couple the compute node to a fabric, the host fabric interface comprising second one or more logic elements comprising a data pulling engine, the data pulling engine to: publish the datum as available; receive a pull request for the datum, the pull request comprising a node identifier for a data consumer; and send the datum to the data consumer via the fabric. There is also disclosed a method of providing a data pulling engine.

公开(公告)号：US20180351812A1

公开(公告)日：2018-12-06

申请号：US15941918

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Eric R. Borch ,  Robert C. Zak ,  Mario Flajslik ,  Jonathan M. Eastep ,  Michael A. Parker

IPC: H04L12/24 ,  H04L12/26

Abstract: Technologies for dynamic bandwidth management of interconnect fabric include a compute device configured to calculate a predicted fabric bandwidth demand which is expected to be used by the interconnect fabric in a next epoch and subsequent to a present epoch. The compute device is additionally configured to determine whether any global links and/or local links of the interconnect fabric can be disabled during the next epoch as a function of the calculated predicted fabric bandwidth demand and a number of redundant paths associated with the links of the interconnect fabric. The compute device is further configured to disable one or more of the global links and/or the local links that can be disabled, the one or more local links of the plurality of local links that can be disabled. Other embodiments are described herein.

公开(公告)号：US20180287954A1

公开(公告)日：2018-10-04

申请号：US15472384

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： James Dinan ,  Sayantan Sur ,  Mario Flajslik ,  Keith D. Underwood

IPC: H04L12/863 ,  H04L12/801 ,  H04L12/919

Abstract: Technologies for offloaded management of communication are disclosed. In order to manage communication with information that may be available to applications in a compute device, the compute device may offload communication management to a host fabric interface using a credit management system. A credit limit is established, and each message to be sent is added to a queue with a corresponding number of credits required to send the message. The host fabric interface of the compute device may send out messages as credits become available and decrease the number of available credits based on the number of credits required to send a particular message. When an acknowledgement of receipt of a message is received, the number of credits required to send the corresponding message may be added back to an available credit pool.

公开(公告)号：US20180234347A1

公开(公告)日：2018-08-16

申请号：US15429716

申请日：2017-02-10

Applicant: INTEL CORPORATION

Inventor： James Dinan ,  Mario Flajslik ,  Robert C. Zak

IPC: H04L12/825 ,  H04L12/26 ,  H04L12/801

CPC classification number: H04L47/25 ,  H04L43/0894 ,  H04L43/10 ,  H04L47/12 ,  H04L47/127 ,  H04L67/1097

Abstract: Technologies for endpoint congestion avoidance are disclosed. In order to avoid congestion caused by a network fabric that can transport data to a compute device faster than the compute device can store the data in a particular type of memory, the compute device may in the illustrative embodiment determine a suitable data transfer rate and communicate an indication of the data transfer rate to the remote compute device which is sending the data. The remote compute device may then send the data at the indicated data transfer rate, thus avoiding congestion.

公开(公告)号：US09916178B2

公开(公告)日：2018-03-13

申请号：US14866572

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： James Dinan ,  Mario Flajslik ,  Tom St. John

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/46 ,  G06F9/4881 ,  G06F9/5027 ,  G06F9/5038 ,  G06F2209/484 ,  G06F2209/485

Abstract: Technologies for integrated thread scheduling include a computing device having a network interface controller (NIC). The NIC is configured to detect and suspend a thread that is being blocked by one or more communication operations. A thread scheduling engine of the NIC is configured to move the suspended thread from a running queue of the system thread scheduler to a pending queue of the thread scheduling engine. The thread scheduling engine is further configured to move the suspended thread from the pending queue to a ready queue of the thread scheduling engine upon determining any dependencies and/or blocking communications operations have completed. Other embodiments are described and claimed.

公开(公告)号：US20170185561A1

公开(公告)日：2017-06-29

申请号：US14757892

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： James Dinan ,  Mario Flajslik ,  Keith Underwood ,  David Keppel ,  Ulf Rainer Hanebutte

IPC: G06F15/167 ,  H04L12/931

CPC classification number: H04L49/35 ,  G06F15/17331

Abstract: In an example, there is disclosed a compute node, comprising: first one or more logic elements comprising a data producer engine to produce a datum; and a host fabric interface to communicatively couple the compute node to a fabric, the host fabric interface comprising second one or more logic elements comprising a data pulling engine, the data pulling engine to: publish the datum as available; receive a pull request for the datum, the pull request comprising a node identifier for a data consumer; and send the datum to the data consumer via the fabric. There is also disclosed a method of providing a data pulling engine.

公开(公告)号：US20170090979A1

公开(公告)日：2017-03-30

申请号：US14866572

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： James Dinan ,  Mario Flajslik ,  Tom St. John

IPC: G06F9/48

CPC classification number: G06F9/46 ,  G06F9/4881 ,  G06F9/5027 ,  G06F9/5038 ,  G06F2209/484 ,  G06F2209/485

Abstract: Technologies for integrated thread scheduling include a computing device having a network interface controller (NIC). The NIC is configured to detect and suspend a thread that is being blocked by one or more communication operations. A thread scheduling engine of the NIC is configured to move the suspended thread from a running queue of the system thread scheduler to a pending queue of the thread scheduling engine. The thread scheduling engine is further configured to move the suspended thread from the pending queue to a ready queue of the thread scheduling engine upon determining any dependencies and/or blocking communications operations have completed. Other embodiments are described and claimed.