公开(公告)号：US10860682B2

公开(公告)日：2020-12-08

申请号：US16839013

申请日：2020-04-02

Applicant: Intel Corporation

Inventor： Phil Knag ,  Gregory K. Chen ,  Raghavan Kumar ,  Huseyin Ekin Sumbul ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC: G06F17/16 ,  G11C11/419 ,  G11C11/418 ,  G11C7/12 ,  G11C8/08 ,  G06G7/16 ,  G06G7/22 ,  G11C11/56 ,  G06F9/30 ,  G11C7/10 ,  G06N3/063

Abstract: A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.

公开(公告)号：US20200334161A1

公开(公告)日：2020-10-22

申请号：US16921685

申请日：2020-07-06

Applicant: Intel Corporation

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC: G06F12/0875 ,  G06N3/063 ,  G06N3/04 ,  G06F3/06 ,  G06F8/41 ,  G06F9/455

Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of in-memory vector/tensor calculations in furtherance of neural network processing without burdening the processor circuitry.

公开(公告)号：US10754619B2

公开(公告)日：2020-08-25

申请号：US16143770

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Sudhir Satpathy ,  Sanu Mathew ,  Vikram Suresh ,  Raghavan Kumar

IPC: G06F7/58 ,  H04L9/32 ,  G06F21/75

Abstract: An embodiment of a semiconductor package apparatus may include technology to provide an entropy extractor including a physically unclonable function (PUF), a true random number generator (TRNG), an entropy source coupled to both the PUF and the TRNG, and a circuit to self-calibrate the entropy extractor. Other embodiments are disclosed and claimed.

公开(公告)号：US10565138B2

公开(公告)日：2020-02-18

申请号：US16146534

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Jack Kavalieros ,  Ram Krishnamurthy ,  Sasikanth Manipatruni ,  Gregory Chen ,  Van Le ,  Amrita Mathuriya ,  Abhishek Sharma ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Sumbul ,  Ian Young

IPC: G11C8/00 ,  G06F13/16 ,  H01L25/18 ,  H03K19/21 ,  G11C11/408 ,  H01L23/522 ,  G11C11/419

Abstract: Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.

公开(公告)号：US10248906B2

公开(公告)日：2019-04-02

申请号：US15392407

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Huseyin E. Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Christopher Knag ,  Ram Krishnamurthy

IPC: G06F15/18 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: A neuromorphic computing system is provided which comprises: a synapse core; and a pre-synaptic neuron, a first post-synaptic neuron, and a second post-synaptic neuron coupled to the synaptic core, wherein the synapse core is to: receive a request from the pre-synaptic neuron, generate, in response to the request, a first address of the first post-synaptic neuron and a second address of the second post-synaptic neuron, wherein the first address and the second address are not stored in the synapse core prior to receiving the request.

公开(公告)号：US20190042913A1

公开(公告)日：2019-02-07

申请号：US15884001

申请日：2018-01-30

Applicant: Intel Corporation

Inventor： Phil Knag ,  Gregory Kengho Chen ,  Raghavan Kumar ,  Huseyin Ekin Sumbul ,  Ram Kumar Krishnamurthy

IPC: G06N3/04

Abstract: Various systems, devices, and methods for operating on a data sequence. A system includes a set of circuits that form an input layer to receive a data sequence; first hardware computing units to transform the data sequence, the first hardware computing units connected using a set of randomly selected weights, a first hardware computing unit to: receive an input from a second hardware computing unit, determine a weight of a connection between the first and second hardware computing units using an identifier of the second hardware computing unit and a fixed random weight generator, and operate on the input using the weight to determine a state of the first hardware computing unit; and second hardware computing units to operate on states of the first computing units to generate an output based on the data sequence.

公开(公告)号：US20190004770A1

公开(公告)日：2019-01-03

申请号：US15637453

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Sudhir K. Satpathy ,  Raghavan Kumar ,  Arvind Singh ,  Vikram B. Suresh ,  Sanu K. Mathew

IPC: G06F7/72 ,  H04L9/32

Abstract: In one embodiment, an apparatus comprises a multiplier circuit to: identify a point multiply operation to be performed by the multiplier circuit, wherein the point multiply operation comprises point multiplication of a first plurality of operands; identify a point add operation associated with the point multiply operation, wherein the point add operation comprises point addition of a second plurality of operands, wherein the second plurality of operands comprises a first point and a second point, and wherein the first point and the second point are associated with a first coordinate system; convert the second point from the first coordinate system to a second coordinate system; perform the point add operation based on the first point associated with the first coordinate system and the second point associated with the second coordinate system; and perform the point multiply operation based on a result of the point add operation.

公开(公告)号：US20180364982A1

公开(公告)日：2018-12-20

申请号：US15627526

申请日：2017-06-20

Applicant: Intel Corporation

Inventor： Sudhir K. Satpathy ,  Sanu K. Mathew ,  Vikram B. Suresh ,  Raghavan Kumar

IPC: G06F7/523 ,  G06F21/72

Abstract: In one embodiment, an apparatus comprises a multiplier circuit to: identify a plurality of partial products associated with a multiply operation; partition the plurality of partial products into a first set of partial products, a second set of partial products, and a third set of partial products; determine whether the multiply operation is associated with a square operation; upon a determination that the multiply operation is associated with the square operation, compute a result based on the first set of partial products and the third set of partial products; and upon a determination that the multiply operation is not associated with the square operation, compute the result based on the first set of partial products, the second set of partial products, and the third set of partial products.

公开(公告)号：US20180189648A1

公开(公告)日：2018-07-05

申请号：US15394976

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Abhronil Sengupta ,  Gregory K. Chen ,  Raghavan Kumar ,  Huseyin Ekin Sumbul ,  Phil Knag

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06N3/049

Abstract: In one embodiment, a processor is to store a membrane potential of a neural unit of a neural network; and calculate, at a particular time-step of the neural network, a change to the membrane potential of the neural unit occurring over multiple time-steps that have elapsed since the last time-step at which the membrane potential was updated, wherein each of the multiple time-steps that have elapsed since the last time-step is associated with at least one input to the neural unit that affects the membrane potential of the neural unit.

公开(公告)号：US20180189646A1

公开(公告)日：2018-07-05

申请号：US15396147

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Huseyin E. Sumbul ,  Gregory K. Chen ,  Phil Knag

IPC: G06N3/063

CPC classification number: G06N3/0635 ,  G06N3/049 ,  G06N3/063

Abstract: Apparatus and method for configuring large numbers of fan-in and fan-out connections in a neuromorphic computer. For example, one embodiment of an apparatus comprises: a plurality of neurons, each neuron uniquely identifiable with a neuron identifier (ID); at least one memory to store neuron addresses with wildcard values to establish fan-in and/or fan-out connections between the neurons; and a router to translate at least one neuron address containing wildcard values into two or more neuron IDs to establish the fan-in and/or fan-out connections between the neurons.