公开(公告)号：US20150293419A1

公开(公告)日：2015-10-15

申请号：US14749132

申请日：2015-06-24

Applicant: Japan Display Inc.

Inventor： Takahiro OCHIAI ,  Motoharu MIYAMOTO ,  Masahiro HOSHIBA

IPC: G02F1/1362 ,  H01L29/786 ,  G02F1/1368

CPC classification number: G02F1/136209 ,  G02F1/133512 ,  G02F1/13454 ,  G02F1/136227 ,  G02F1/1368 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0809 ,  G09G2310/0202 ,  H01L27/1222 ,  H01L27/124 ,  H01L29/78609 ,  H01L29/78633 ,  H01L29/78669

Abstract: A liquid crystal display device is provided with a thin film transistor which includes a gate electrode film that is provided in a first electrode layer located over a first insulating layer, a semiconductor film that is disposed over the gate electrode film via a second insulating layer, a drain electrode and a source electrode that are provided in a second electrode layer located over the semiconductor film and are in contact with an upper surface of the semiconductor film, and a light blocking film that is disposed under the first insulating layer. At least a part thereof overlaps the semiconductor film and the gate electrode film in a plan view. One of the drain electrode and the source electrode is connected to a gate line, and the light blocking film is electrically connected to the source electrode.

Abstract translation: 液晶显示装置设置有薄膜晶体管，该薄膜晶体管包括设置在位于第一绝缘层上的第一电极层中的栅极电极膜，经由第二绝缘层设置在栅电极膜上的半导体膜， 漏电极和源极，设置在位于所述半导体膜上方并与所述半导体膜的上表面接触的第二电极层中，以及设置在所述第一绝缘层下方的遮光膜。 其至少一部分在平面图中与半导体膜和栅电极膜重叠。 漏电极和源电极之一连接到栅极线，并且遮光膜与源电极电连接。

公开(公告)号：US20150091887A1

公开(公告)日：2015-04-02

申请号：US14497388

申请日：2014-09-26

Applicant: Japan Display Inc.

Inventor： Takahiro OCHIAI ,  Motoharu MIYAMOTO ,  Masahiro HOSHIBA

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G11C19/28

Abstract: A gate signal line drive circuit whose power consumption is reduced, is provided. In the gate signal line drive circuit having plural basic circuits outputting respective gate signals, each basic circuit includes a high voltage application switching element to which a first basic clock signal having high voltage in a signal high period is input, a low voltage application switching element that turns on at timing starting a signal low period, and outputs a low voltage, and a first low voltage application on control element having an input terminal to which a second basic clock signal subsequent to the first basic clock signal is input, and which turns on according to the signal high period, and outputs the voltage of the second basic clock signal to the control terminal of the low voltage application switching element.

Abstract translation: 提供功耗降低的门信号线驱动电路。 在具有输出各个门信号的多个基本电路的栅极信号线驱动电路中，每个基本电路包括高电压施加开关元件，输入信号高电平的高电压的第一基本时钟信号，低电压施加开关元件 在定时启动信号低电平周期时接通，并且在输入有第一基本时钟信号之后的第二基本时钟信号的输入端子的控制元件上输出低电压和第一低电压施加，并且转向 根据信号高周期导通，并将第二基本时钟信号的电压输出到低电压应用开关元件的控制端子。

公开(公告)号：US20140204010A1

公开(公告)日：2014-07-24

申请号：US14161723

申请日：2014-01-23

Applicant: Japan Display Inc.

Inventor： Motoharu MIYAMOTO ,  Takahiro OCHIAI

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G02F1/13306 ,  G02F1/1345 ,  G09G3/2096 ,  G09G2300/0426 ,  G09G2300/0809 ,  G09G2310/0202 ,  G09G2310/065

Abstract: A circuit block of a driving circuit of a display device includes a first transistor that has a gate being connected to a first node having an active potential during an output period, and controls electrical conduction between a first clock signal line being applied with a first clock signal and the scanning signal line, a second transistor that has a gate being connected to a second node having an active potential during a non-output period, and controls electrical conduction between the first node and an inactive potential line, and a third transistor that has a gate being connected to the first node, and controls electrical conduction between the second node and a first cyclic signal line applied with a first period signal having an active potential at the time of termination of the output period.

Abstract translation: 显示装置的驱动电路的电路块包括第一晶体管，其在输出周期期间具有连接到具有有效电位的第一节点的栅极，并且控制施加于第一时钟的第一时钟信号线之间的导通 信号和扫描信号线，第二晶体管，其在非输出时段期间具有连接到具有有效电位的第二节点的栅极，并控制第一节点与非活动电位线之间的电导;以及第三晶体管， 具有连接到第一节点的栅极，并且控制第二节点与施加在输出周期结束时具有有效电位的第一周期信号的第一循环信号线之间的导电。