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    DISPLAY ELEMENT HAVING GROUPS OF INDIVIDUALLY TURNED-ON STEPS
    41.
    发明申请
    DISPLAY ELEMENT HAVING GROUPS OF INDIVIDUALLY TURNED-ON STEPS 有权
    具有单独开启步骤的组合的显示元件

    公开(公告)号：US20100045582A1

    公开(公告)日：2010-02-25

    申请号：US12374977

    申请日：2007-07-19

    申请人： Peter Fricke ,  Alan R. Arthur ,  Joseph Stellbrink ,  Tim R. Koch

    发明人： Peter Fricke ,  Alan R. Arthur ,  Joseph Stellbrink ,  Tim R. Koch

    IPC分类号： G09G3/36

    CPC分类号： G09G3/364 ,  G02F1/133371 ,  G02F1/1391 ,  G02F2001/134345 ,  G09G3/3637

    摘要： A display element (100) corresponds to a pixel of a display. The display element includes a top electrode (102) connected to a first addressable line of the display, and a bottom electrode (104) connected to a second addressable line of the display. The display element includes a display mechanism (106) situated between the top electrode and the bottom electrode and having a number of individually turned-on steps. Each individually turned-on step has a turn-on voltage threshold at which the step is turned on upon a voltage applied between the top and the bottom electrodes equal to or greater than the turn-on voltage threshold. Each individually turned-on step has a turn-off voltage threshold at which the step is turned off upon a voltage applied between the top and the bottom electrodes equal to or less than the turn-off voltage threshold.

    摘要翻译： 显示元件（100）对应于显示器的像素。 显示元件包括连接到显示器的第一可寻址线路的顶部电极（102）和连接到显示器的第二可寻址线路的底部电极（104）。 显示元件包括位于顶部电极和底部电极之间并具有多个单独接通步骤的显示机构（106）。 每个单独导通步骤具有接通电压阈值，在施加在顶部电极和底部电极之间的电压等于或大于导通电压阈值时，该步骤被接通。 每个单独导通步骤具有截止电压阈值，在该阈值处，在施加在顶部和底部电极之间的电压等于或小于关断电压阈值时，该步骤被关断。

    Methods and memory structures using tunnel-junction device as control element
    43.
    发明授权
    Methods and memory structures using tunnel-junction device as control element 失效
    使用隧道结装置作为控制元件的方法和记忆结构

    公开(公告)号：US07372714B2

    公开(公告)日：2008-05-13

    申请号：US11494397

    申请日：2006-07-26

    申请人： Peter Fricke ,  Andrew L. Van Brocklin ,  James E. Ellenson

    发明人： Peter Fricke ,  Andrew L. Van Brocklin ,  James E. Ellenson

    IPC分类号： G11C5/02

    CPC分类号： G11C13/003 ,  G11C17/16 ,  G11C17/18 ,  G11C2213/76

    摘要： A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A reference element comprising a tunnel-junction device may be used with a current source to fuse a memory storage element without fusing a tunnel-junction device of an associated control element. Methods of making the memory structure and using it in electronic devices are disclosed.

    摘要翻译： 存储器结构包括电耦合到控制元件的存储器存储元件。 控制元件包括隧道连接装置。 存储器存储元件还可以包括隧道连接装置。 公开了一种用于熔接存储器存储元件的隧道结器件而不熔接相关控制元件的隧道结器件的方法。 存储器存储元件可以具有大于控制元件的有效横截面面积的有效横截面面积。 包括隧道结结器件的参考元件可以与电流源一起使用，以熔化存储器存储元件而不熔合相关联的控制元件的隧道连接器件。 公开了在电子设备中制作存储器结构并将其使用的方法。

    Memory storage device with segmented column line array
    48.
    发明授权
    Memory storage device with segmented column line array 有权
    具有分段列线阵列​​的内存存储设备

    公开(公告)号：US06917532B2

    公开(公告)日：2005-07-12

    申请号：US10177596

    申请日：2002-06-21

    申请人： Andrew L. Van Brocklin ,  Peter Fricke

    发明人： Andrew L. Van Brocklin ,  Peter Fricke

    IPC分类号： H01L27/112 ,  G11C5/02 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/24

    CPC分类号： G11C5/025 ,  H01L27/24

    摘要： A memory storage device includes a first and second memory cell which each have a top end and a bottom end. A first and second first dimension conductor are substantially coplanar and parallel and extend in a first dimension. The first first dimension conductor intersects the bottom end of the first memory cell and the second first dimension conductor intersects the top end of the second memory cell. A first second dimension conductor extends in a second dimension and intersects the top end of the first memory cell and a second second dimension conductor extends in the second dimension and intersects the bottom end of the second memory cell. A first third dimension conductor which extends in a third dimension is positioned between the first and second memory cell to couple the first second dimension conductor to the second second dimension conductor.

    摘要翻译： 存储器存储装置包括第一和第二存储单元，每个具有顶端和底端。 第一和第二第一尺寸导体基本共面并平行并且在第一维度上延伸。 第一第一尺寸导体与第一存储单元的底端相交，并且第二第一尺寸导体与第二存储单元的顶端相交。 第一第二尺寸导体在第二维度上延伸并与第一存储单元的顶端相交，而第二尺寸导体在第二维度上延伸并与第二存储单元的底端相交。 在第三维度上延伸的第一第三尺寸导体位于第一和第二存储单元之间，以将第一第二尺寸导体耦合到第二第二尺寸导体。

    Methods and memory structures using tunnel-junction device as control element
    50.
    发明授权
    Methods and memory structures using tunnel-junction device as control element 失效

    公开(公告)号：US06711045B2

    公开(公告)日：2004-03-23

    申请号：US10236274

    申请日：2002-09-06

    申请人： Peter Fricke ,  Andrew L. Van Brocklin ,  James E. Ellenson

    发明人： Peter Fricke ,  Andrew L. Van Brocklin ,  James E. Ellenson

    IPC分类号： G11C506

    CPC分类号： H01L27/224 ,  G11C17/18 ,  H01L27/2418 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/06 ,  H01L45/1226

    摘要： A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element. The reference element may comprise a tunnel-junction device and be used with a current source to fuse a memory storage element without fusing a tunnel-junction device of an associated control element. Methods of making the memory structure and using it in electronic devices are disclosed.