公开(公告)号：US07130207B2

公开(公告)日：2006-10-31

申请号：US10756661

申请日：2004-01-12

申请人： Peter Fricke ,  Andrew L. Van Brocklin ,  James E. Ellenson

发明人： Peter Fricke ,  Andrew L. Van Brocklin ,  James E. Ellenson

IPC分类号： G11C5/02

CPC分类号： G11C13/003 ,  G11C17/16 ,  G11C17/18 ,  G11C2213/76

摘要： A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element. The reference element may comprise a tunnel-junction device and be used with a current source to fuse a memory storage element without fusing a tunnel-junction device of an associated control element. Methods of making the memory structure and using it in electronic devices are disclosed.

公开(公告)号：US06821848B2

公开(公告)日：2004-11-23

申请号：US10286157

申请日：2002-10-30

申请人： Dennis Lazaroff ,  Kenneth M. Kramer ,  James E. Ellenson ,  Neal W. Meyer ,  David Punsalan ,  Kurt Ulmer ,  Peter Fricke ,  Andrew Koll ,  Andrew L. Van Brocklin

发明人： Dennis Lazaroff ,  Kenneth M. Kramer ,  James E. Ellenson ,  Neal W. Meyer ,  David Punsalan ,  Kurt Ulmer ,  Peter Fricke ,  Andrew Koll ,  Andrew L. Van Brocklin

IPC分类号： H01L21336

CPC分类号： G11C13/003 ,  G11C17/16 ,  G11C17/18 ,  G11C2213/76

摘要： Tunnel-junction structures are fabricated by any of a set of related methods that form two or more tunnel junctions simultaneously. The fabrication methods disclosed are compatible with conventional CMOS fabrication practices, including both single damascene and dual damascene processes. The simultaneously formed tunnel junctions may have different areas. In some embodiments, tub-well structures are formed with sloped sidewalls. In some embodiments, an oxide-metal-oxide film stack on the sidewall of a tub-well is etched to form the tunnel junctions. Memory circuits, other integrated circuit structures, substrates carrying microelectronics, and other electronic devices made by the methods are disclosed.

摘要翻译： 隧道结结构通过同时形成两个或更多个隧道结的一组相关方法中的任一种来制造。 所公开的制造方法与常规CMOS制造实践兼容，包括单镶嵌和双镶嵌工艺。 同时形成的隧道结可以具有不同的区域。 在一些实施例中，浴盆结构形成有倾斜的侧壁。 在一些实施例中，蚀刻在浴缸的侧壁上的氧化物 - 金属氧化物膜堆叠以形成隧道结。 公开了存储电路，其它集成电路结构，携带微电子的衬底以及通过该方法制造的其它电子器件。

公开(公告)号：US06831861B2

公开(公告)日：2004-12-14

申请号：US10756450

申请日：2004-01-12

申请人： Peter Fricke ,  Andrew L. Van Brocklin ,  James E. Ellenson

发明人： Peter Fricke ,  Andrew L. Van Brocklin ,  James E. Ellenson

IPC分类号： G11C700

CPC分类号： G11C13/003 ,  G11C17/16 ,  G11C17/18 ,  G11C2213/76

摘要： A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element. The reference element may comprise a tunnel-junction device and be used with a current source to fuse a memory storage element without fusing a tunnel-junction device of an associated control element. Methods of making the memory structure and using it in electronic devices are disclosed.

公开(公告)号：US07372714B2

公开(公告)日：2008-05-13

申请号：US11494397

申请日：2006-07-26

申请人： Peter Fricke ,  Andrew L. Van Brocklin ,  James E. Ellenson

发明人： Peter Fricke ,  Andrew L. Van Brocklin ,  James E. Ellenson

IPC分类号： G11C5/02

CPC分类号： G11C13/003 ,  G11C17/16 ,  G11C17/18 ,  G11C2213/76

摘要： A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A reference element comprising a tunnel-junction device may be used with a current source to fuse a memory storage element without fusing a tunnel-junction device of an associated control element. Methods of making the memory structure and using it in electronic devices are disclosed.

摘要翻译： 存储器结构包括电耦合到控制元件的存储器存储元件。 控制元件包括隧道连接装置。 存储器存储元件还可以包括隧道连接装置。 公开了一种用于熔接存储器存储元件的隧道结器件而不熔接相关控制元件的隧道结器件的方法。 存储器存储元件可以具有大于控制元件的有效横截面面积的有效横截面面积。 包括隧道结结器件的参考元件可以与电流源一起使用，以熔化存储器存储元件而不熔合相关联的控制元件的隧道连接器件。 公开了在电子设备中制作存储器结构并将其使用的方法。

公开(公告)号：US06711045B2

公开(公告)日：2004-03-23

申请号：US10236274

申请日：2002-09-06

申请人： Peter Fricke ,  Andrew L. Van Brocklin ,  James E. Ellenson

发明人： Peter Fricke ,  Andrew L. Van Brocklin ,  James E. Ellenson

IPC分类号： G11C506

CPC分类号： H01L27/224 ,  G11C17/18 ,  H01L27/2418 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/06 ,  H01L45/1226

摘要： A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element. The reference element may comprise a tunnel-junction device and be used with a current source to fuse a memory storage element without fusing a tunnel-junction device of an associated control element. Methods of making the memory structure and using it in electronic devices are disclosed.

公开(公告)号：US06781858B2

公开(公告)日：2004-08-24

申请号：US10650895

申请日：2003-08-29

申请人： Peter Fricke ,  Andrew L. Van Brocklin ,  Daryl Anderson

发明人： Peter Fricke ,  Andrew L. Van Brocklin ,  Daryl Anderson

IPC分类号： G11C502

CPC分类号： H01L21/8221 ,  G11C5/025 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/249 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

摘要： A cubic memory array is fabricated on a substrate having a planar surface. The cubic memory array includes a plurality of first select-lines organized in more than one plane parallel to the planar surface. A plurality of second select-lines is formed in pillars disposed orthogonal to the planer surface of the substrate. A plurality of memory cells are respectively coupled to the plurality of first and plurality of second select-lines.

摘要翻译： 在具有平坦表面的基板上制造立方体存储器阵列。 立方体存储器阵列包括多个第一选择线，其组织在平行于平面的多个平面中。 多个第二选择线形成在垂直于基板的平面的柱上。 多个存储单元分别耦合到多个第一和第二选择线。

公开(公告)号：US06717215B2

公开(公告)日：2004-04-06

申请号：US10177240

申请日：2001-06-21

申请人： Peter Fricke ,  Andrew L. Van Brocklin ,  Andrew Koll

发明人： Peter Fricke ,  Andrew L. Van Brocklin ,  Andrew Koll

IPC分类号： H01L2712

CPC分类号： H01L45/085 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/148 ,  H01L45/1633

摘要： A memory structure that includes a first electrode, a second electrode, a thermal conduction limiting electrode having a thermal conductivity that is less than a thermal conductivity of the first electrode, a memory storage elementdisposed between the thermal conduction limiting electrode and the second electrode, and a control element disposed between the second electrode and the first electrode.

摘要翻译： 一种存储器结构，包括第一电极，第二电极，导热率小于第一电极的热导率的导热限制电极，布置在导热限制电极和第二电极之间的存储器存储元件，以及 设置在所述第二电极和所述第一电极之间的控制元件。

公开(公告)号：US06643159B2

公开(公告)日：2003-11-04

申请号：US10116213

申请日：2002-04-02

申请人： Peter Fricke ,  Andrew L. Van Brocklin ,  Daryl Anderson

发明人： Peter Fricke ,  Andrew L. Van Brocklin ,  Daryl Anderson

IPC分类号： G11C502

CPC分类号： H01L21/8221 ,  G11C5/025 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/249 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

摘要： A cubic memory array is fabricated on a substrate having a planar surface. The cubic memory array includes a plurality of first select-lines organized in more than one plane parallel to the planar surface. A plurality of second select-lines is formed in pillars disposed orthogonal to the planer surface of the substrate. A plurality of memory cells are respectively coupled to the plurality of first and plurality of second select-lines.

摘要翻译： 在具有平坦表面的基板上制造立方体存储器阵列。 立方体存储器阵列包括多个第一选择线，其组织在平行于平面的多个平面中。 多个第二选择线形成在垂直于基板的平面的柱上。 多个存储单元分别耦合到多个第一和第二选择线。

公开(公告)号：US06559516B1

公开(公告)日：2003-05-06

申请号：US10051676

申请日：2002-01-16

申请人： Andrew L. Van Brocklin ,  Peter Fricke

发明人： Andrew L. Van Brocklin ,  Peter Fricke

IPC分类号： H01L2900

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： An antifuse structure has an antifuse between first and second thermal conduction regions. Each of the first and second thermal conduction regions has a portion of low thermal conductivity and a portion of high thermal conductivity. The portion having low thermal conductivity is between the respective portion of high thermal conductivity and the antifuse.

摘要翻译： 反熔丝结构在第一和第二导热区域之间具有反熔丝。 第一和第二导热区域中的每一个具有低热导率的部分和高导热率的一部分。 具有低热导率的部分在高热导率的相应部分和反熔丝之间。

公开(公告)号：US06958946B2

公开(公告)日：2005-10-25

申请号：US10264153

申请日：2002-10-02

申请人： Andrew L. Van Brocklin ,  Peter Fricke ,  John M. da Cunha

发明人： Andrew L. Van Brocklin ,  Peter Fricke ,  John M. da Cunha

IPC分类号： G11C7/06 ,  G11C7/08 ,  G11C7/14 ,  G11C17/16 ,  G11C17/18 ,  H01L27/10 ,  G11C5/14

CPC分类号： G11C7/06 ,  G11C7/14 ,  G11C17/16 ,  G11C17/18

摘要： A memory storage device includes a memory cell configurable to have at least a first conductive state and includes a first and second conductor each electrically coupled to the memory cell. A regulation circuit is configured to regulate a sense voltage on the second conductor to be independent of a current conducted through the first conductor when the memory cell is configured to have the first conductive state.

摘要翻译： 存储器存储器件包括可配置为具有至少第一导电状态并且包括电耦合到存储器单元的第一和第二导体的存储单元。 调节电路被配置为当存储单元被配置为具有第一导通状态时，调节第二导体上的感测电压，以独立于通过第一导体传导的电流。