公开(公告)号：US10164905B2

公开(公告)日：2018-12-25

申请号：US14608265

申请日：2015-01-29

Applicant: Mellanox Technologies Ltd.

Inventor： Ofer Hayut ,  Noam Bloch ,  Shlomo Raikin ,  Liran Liss

IPC: H04L12/803 ,  H04L12/721 ,  H04L12/931

Abstract: A Network Interface Controller (NIC) includes a network interface, a peer interface and steering logic. The network interface is configured to receive incoming packets from a communication network. The peer interface is configured to communicate with a peer NIC not via the communication network. The steering logic is configured to classify the packets received over the network interface into first incoming packets that are destined to a local Central Processing Unit (CPU) served by the NIC, and second incoming packets that are destined to a remote CPU served by the peer NIC, to forward the first incoming packets to the local CPU, and to forward the second incoming packets to the peer NIC over the peer interface not via the communication network.

公开(公告)号：US10082858B2

公开(公告)日：2018-09-25

申请号：US14745549

申请日：2015-06-22

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Idan Burstein ,  Shlomo Raikin ,  Noam Bloch

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3209

Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having multiple host resources, information regarding respective power states of the host resources. The data are selectively directed from the peripheral device to the host resources responsively to the respective power states.

公开(公告)号：US20180102976A1

公开(公告)日：2018-04-12

申请号：US15836869

申请日：2017-12-10

Applicant: Mellanox Technologies, Ltd.

Inventor： Michael Kagan ,  Noam Bloch

IPC: H04L12/851 ,  H04L29/00 ,  G06F13/30

Abstract: A network interface controller includes a host interface, which is configured to be coupled to a host processor having a host memory. A network interface is configured to receive data packets from a network, each data packet including a header, which includes header fields, and a payload including data. Packet processing circuitry is configured to process one or more of the header fields and at least a part of the data and to select, responsively at least to the one or more of the header fields, a location in the host memory. The circuitry writes the data to the selected location and upon determining that the processed data satisfies a predefined criterion, asserts an interrupt on the host processor so as to cause the host processor to read the data from the selected location in the host memory.

公开(公告)号：US09639464B2

公开(公告)日：2017-05-02

申请号：US13628155

申请日：2012-09-27

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Haggai Eran ,  Shachar Raindel ,  Liran Liss ,  Noam Bloch

IPC: G06F12/08 ,  G06F12/1081

CPC classification number: G06F12/08 ,  G06F12/1081

Abstract: A method for data transfer includes receiving in an operating system of a host computer an instruction initiated by a user application running on the host processor identifying a page of virtual memory of the host computer that is to be used in receiving data in a message that is to be transmitted over a network to the host computer but has not yet been received by the host computer. In response to the instruction, the page is loaded into the memory, and upon receiving the message, the data are written to the loaded page.

公开(公告)号：US09344490B2

公开(公告)日：2016-05-17

申请号：US14324246

申请日：2014-07-07

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Noam Bloch ,  Gil Bloch ,  Ariel Shachar ,  Hillel Chapman ,  Ishai Rabinobitz ,  Pavel Shamis ,  Gilad Shainer

IPC: G06F9/54 ,  H04L29/08

CPC classification number: H04L67/10 ,  G06F9/546 ,  G06F2209/509

Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

Abstract translation: 网络接口（NI）包括主机接口，其被配置为从节点的主机处理器接收从要由节点执行的操作导出的一个或多个跨通道工作请求。 NI包括用于通过网络向一个或多个对等节点执行传输信道的多个工作队列。 NI还包括控制电路，其被配置为经由主机接口接受跨通道工作请求，并且通过根据一个或多个控制电路控制至少一个给定的工作队列的前进来执行使用工作队列的跨通道工作请求 这取决于一个或多个其他工作队列的完成状态，以便执行操作。

公开(公告)号：US20160065659A1

公开(公告)日：2016-03-03

申请号：US14937907

申请日：2015-11-11

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Noam Bloch ,  Gil Bloch ,  Ariel Shahar ,  Hillel Chapman ,  Gilad Shainer ,  Adi Menachem ,  Ofer Hayut

IPC: H04L29/08

CPC classification number: H04L67/10 ,  G06F9/546 ,  G06F2209/509

Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more work requests that are derived from an operation to be executed by the node. The NI maintains a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the work requests via the host interface, and to execute the work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

Abstract translation: 网络接口（NI）包括主机接口，其被配置为从节点的主处理器接收从要由该节点执行的操作导出的一个或多个工作请求。 NI维护多个工作队列，用于通过网络向一个或多个对等节点执行传输信道。 NI还包括控制电路，其被配置为通过主机接口接受工作请求，并且通过根据前进条件控制至少给定的工作队列的进度来执行工作请求，所述进展条件取决于 一个或多个其他工作队列的完成状态，以便执行操作。

公开(公告)号：US20150370309A1

公开(公告)日：2015-12-24

申请号：US14745549

申请日：2015-06-22

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Idan Burstein ,  Shlomo Raikin ,  Noam Bloch

IPC: G06F1/32

CPC classification number: G06F1/3209

Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having multiple host resources, information regarding respective power states of the host resources. The data are selectively directed from the peripheral device to the host resources responsively to the respective power states.

Abstract translation: 一种用于处理数据的方法包括在通过总线连接到具有多个主机资源的主机处理器的外围设备中接收关于主机资源的各自的电力状态的信息。 响应于各自的功率状态，数据被选择性地从外围设备引导到主机资源。

公开(公告)号：US20150261434A1

公开(公告)日：2015-09-17

申请号：US14215099

申请日：2014-03-17

Applicant: Mellanox Technologies Ltd.

Inventor： Michael Kagan ,  Noam Bloch ,  Shlomo Raikin ,  Yaron Haviv ,  Idan Burstein

IPC: G06F3/06 ,  H04L29/08

CPC classification number: G06F13/28 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0688 ,  G06F13/4221 ,  G06F15/17331 ,  H04L67/10 ,  Y02D10/14 ,  Y02D10/151

Abstract: A data storage system includes a storage server, including non-volatile memory (NVM) and a server network interface controller (NIC), which couples the storage server to a network. A host computer includes a host central processing unit (CPU), a host memory and a host NIC, which couples the host computer to the network. The host computer runs a driver program that is configured to receive, from processes running on the host computer, commands in accordance with a protocol defined for accessing local storage devices connected to a peripheral component interface bus of the host computer, and upon receiving a storage access command in accordance with the protocol, to initiate a remote direct memory access (RDMA) operation to be performed by the host and server NICs so as to execute on the storage server, via the network, a storage transaction specified by the command.

Abstract translation: 数据存储系统包括存储服务器，其包括非易失性存储器（NVM）和将存储服务器耦合到网络的服务器网络接口控制器（NIC）。 主计算机包括主机中央处理单元（CPU），主机存储器和主机NIC，其将主计算机耦合到网络。 主计算机运行驱动程序，其被配置为从主机计算机上运行的进程接收根据为访问连接到主计算机的外围组件接口总线的本地存储设备而定义的协议的命令，以及在接收到存储器 访问命令，以启动由主机和服务器NIC执行的远程直接存储器访问（RDMA）操作，以便经由网络在存储服务器上执行由该命令指定的存储事务。

公开(公告)号：US20150212817A1

公开(公告)日：2015-07-30

申请号：US14608252

申请日：2015-01-29

Applicant: Mellanox Technologies, Ltd.

Inventor： Shlomo Raikin ,  Noam Bloch ,  Richard Graham ,  Ofer Hayut ,  Michael Kagan ,  Liran Liss

IPC: G06F9/30 ,  G06F11/22 ,  G06F11/36

CPC classification number: G06F11/073 ,  G06F9/30043 ,  G06F11/0745 ,  G06F11/0757 ,  G06F11/2236 ,  G06F11/3668

Abstract: A method for network access of remote memory directly from a local instruction stream using conventional loads and stores. In cases where network IO access (a network phase) cannot overlap a compute phase, a direct network access from the instruction stream greatly decreases latency in CPU processing. The network is treated as yet another memory that can be directly read from, or written to, by the CPU. Network access can be done directly from the instruction stream using regular loads and stores. Example scenarios where synchronous network access can be beneficial are SHMEM (symmetric hierarchical memory access) usages (where the program directly reads/writes remote memory), and scenarios where part of system memory (for example DDR) can reside over a network and made accessible by demand to different CPUs.

Abstract translation: 一种使用常规负载和存储直接从本地指令流网络访问远程存储器的方法。 在网络IO访问（网络阶段）不能与计算阶段重叠的情况下，来自指令流的直接网络访问大大降低了CPU处理中的延迟。 该网络被视为可以直接从CPU读取或写入的另一个存储器。 网络访问可以直接从指令流使用常规的负载和存储。 同步网络访问可能有益的示例场景是SHMEM（对称分层存储器访问）用途（程序直接读/写远程内存的位置）以及系统内存（例如DDR）的一部分可以驻留在网络上并使其可访问的情况 通过需求到不同的CPU。

公开(公告)号：US20140143454A1

公开(公告)日：2014-05-22

申请号：US13682772

申请日：2012-11-21

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Ofer Hayut ,  Noam Bloch ,  Michael Kagan ,  Ariel Shachar

IPC: G06F3/01

CPC classification number: G06F3/016 ,  G06F13/128 ,  G06F13/14

Abstract: A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to write completion reports to the system memory, including first completion reports of a first data size and second completion reports of a second data size, which is smaller than the first data size.

Abstract translation: 计算机外围设备包括主机接口，其被配置为通过总线与主处理器和主机处理器的系统存储器进行通信。 外围设备中的处理电路被配置为通过在主处理器上运行的客户端进程来接收和执行提交给外围设备的工作项目，并响应于完成工作项目的执行，将完成报告写入系统存储器，包括首次完成 报告第一数据大小和第二数据大小的第二完成报告，其小于第一数据大小。