公开(公告)号：US20230170033A1

公开(公告)日：2023-06-01

申请号：US17987780

申请日：2022-11-15

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Luyen Vu ,  Lawrence Celso Miranda ,  Jeffrey Ming-Hung Tsai

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/26 ,  G11C16/102

Abstract: Control logic in a memory device initiates a first loop of a program operation, the first loop comprising (a) a program phase where a plurality of memory cells associated with a selected wordline in a block of the memory array are programmed to respective ones of a plurality of programming levels and (b) a corresponding program verify phase. The control logic further identifies memory cells of the plurality of memory cells associated with a first sub-set of the plurality of programming levels to be verified during the program verify phase, the first sub-set comprising two or more dynamically selected programming levels comprising at least a lowest programming level and a second lowest programing level of the respective ones of the plurality of programming levels. The control logic further causes a first program verify voltage to be applied to the selected wordline during the program verify phase, and performs concurrent sensing operations on the identified memory cells of the plurality of memory cells associated with the first sub-set of the plurality programming levels to determine whether the identified memory cells were programmed to respective program verify threshold voltages corresponding to the first sub-set of the plurality of programming levels during the program phase of the first loop of the program operation.

公开(公告)号：US11462281B1

公开(公告)日：2022-10-04

申请号：US17307443

申请日：2021-05-04

Applicant: Micron Technology, Inc.

Inventor： Lawrence Celso Miranda ,  Eric N. Lee ,  Tong Liu ,  Sheyang Ning ,  Cobie B. Loper ,  Ugo Russo

IPC: G11C16/12 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/06

Abstract: Control logic in a memory device identifies a first group of wordlines associated with a first subset of memory cells of a set of memory cells to be programmed. A first dynamic start voltage operation including a first set of programming pulses and a first set of program verify operations is executed on a first portion of the first subset of memory cells to identify a first dynamic start voltage level, the executing of the first dynamic start voltage operation includes causing the first set of programming pulses to be applied to at least a portion of the first group of wordlines. A second set of programming pulses including at least one programming pulse having the first dynamic start voltage level are caused to be applied to the first group of wordlines to program a second portion of the first subset of memory cells of the set of memory cells. A second group of wordlines associated with a second subset of memory cells to be programmed is identified. A second dynamic start voltage operation including a third set of programming pulses and a second set of program verify operations are executed on a first portion of the second subset of memory cells to identify a second dynamic start voltage level.