公开(公告)号：US11462281B1

公开(公告)日：2022-10-04

申请号：US17307443

申请日：2021-05-04

Applicant: Micron Technology, Inc.

Inventor： Lawrence Celso Miranda ,  Eric N. Lee ,  Tong Liu ,  Sheyang Ning ,  Cobie B. Loper ,  Ugo Russo

IPC: G11C16/12 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/06

Abstract: Control logic in a memory device identifies a first group of wordlines associated with a first subset of memory cells of a set of memory cells to be programmed. A first dynamic start voltage operation including a first set of programming pulses and a first set of program verify operations is executed on a first portion of the first subset of memory cells to identify a first dynamic start voltage level, the executing of the first dynamic start voltage operation includes causing the first set of programming pulses to be applied to at least a portion of the first group of wordlines. A second set of programming pulses including at least one programming pulse having the first dynamic start voltage level are caused to be applied to the first group of wordlines to program a second portion of the first subset of memory cells of the set of memory cells. A second group of wordlines associated with a second subset of memory cells to be programmed is identified. A second dynamic start voltage operation including a third set of programming pulses and a second set of program verify operations are executed on a first portion of the second subset of memory cells to identify a second dynamic start voltage level.

公开(公告)号：US12142311B2

公开(公告)日：2024-11-12

申请号：US17829046

申请日：2022-05-31

Applicant: Micron Technology, Inc.

Inventor： Tong Liu ,  Daniele Vimercati

IPC: G11C11/22

Abstract: Systems and methods are related to a memory device including a plate line. The memory device also includes a pair of ferroelectric layers implementing a pair of memory cells and coupled to opposite sides of the plate line. The memory device further includes a pair of digit lines each coupled to a respective ferroelectric layer of the pair of ferroelectric layers. The memory device also includes a sense amplifier coupled to the pair of digit lines and configured to sense and amplify voltages received at the digit lines from the respective memory cells. The sense amplifier includes a threshold voltage compensated latch that includes multiple p-channel transistors and is configured to compensate for process, voltage, or temperature variation mismatches between the threshold voltages of the multiple p-channel transistors.

公开(公告)号：US20250054531A1

公开(公告)日：2025-02-13

申请号：US18930833

申请日：2024-10-29

Applicant: Micron Technology, Inc.

Inventor： Tong Liu ,  Daniele Vimercati

IPC: G11C11/22

Abstract: Systems and methods are related to a memory device including a plate line. The memory device also includes a pair of ferroelectric layers implementing a pair of memory cells and coupled to opposite sides of the plate line. The memory device further includes a pair of digit lines each coupled to a respective ferroelectric layer of the pair of ferroelectric layers. The memory device also includes a sense amplifier coupled to the pair of digit lines and configured to sense and amplify voltages received at the digit lines from the respective memory cells. The sense amplifier includes a threshold voltage compensated latch that includes multiple p-channel transistors and is configured to compensate for process, voltage, or temperature variation mismatches between the threshold voltages of the multiple p-channel transistors.

公开(公告)号：US11664079B2

公开(公告)日：2023-05-30

申请号：US17940338

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Lawrence Celso Miranda ,  Eric N. Lee ,  Tong Liu ,  Sheyang Ning ,  Cobie B. Loper ,  Ugo Russo

IPC: G11C16/12 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/06

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/06

Abstract: Control logic in a memory device executes a first operation comprising a first set of programming pulses and a first set of program verify operations on a first portion of a first subset of memory cells to be programmed to identify a first start voltage level. A second set of programming pulses including at least one programming pulse having the first start voltage level is caused to be applied to program a second portion of the first subset of memory cells. A second operation including a third set of programming pulses and a second set of program verify operations are executed on a first portion of the second subset of memory cells to identify a second start voltage level.

公开(公告)号：US20230005553A1

公开(公告)日：2023-01-05

申请号：US17940338

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Lawrence Celso Miranda ,  Eric N. Lee ,  Tong Liu ,  Sheyang Ning ,  Cobie B. Loper ,  Ugo Russo

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04

Abstract: Control logic in a memory device executes a first operation comprising a first set of programming pulses and a first set of program verify operations on a first portion of a first subset of memory cells to be programmed to identify a first start voltage level. A second set of programming pulses including at least one programming pulse having the first start voltage level is caused to be applied to program a second portion of the first subset of memory cells. A second operation including a third set of programming pulses and a second set of program verify operations are executed on a first portion of the second subset of memory cells to identify a second start voltage level.

公开(公告)号：US20230386545A1

公开(公告)日：2023-11-30

申请号：US17829046

申请日：2022-05-31

Applicant: Micron Technology, Inc.

Inventor： Tong Liu ,  Daniele Vimercati

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221

Abstract: Systems and methods are related to a memory device including a plate line. The memory device also includes a pair of ferroelectric layers implementing a pair of memory cells and coupled to opposite sides of the plate line. The memory device further includes a pair of digit lines each coupled to a respective ferroelectric layer of the pair of ferroelectric layers. The memory device also includes a sense amplifier coupled to the pair of digit lines and configured to sense and amplify voltages received at the digit lines from the respective memory cells. The sense amplifier includes a threshold voltage compensated latch that includes multiple p-channel transistors and is configured to compensate for process, voltage, or temperature variation mismatches between the threshold voltages of the multiple p-channel transistors.

公开(公告)号：US10971500B2

公开(公告)日：2021-04-06

申请号：US16433966

申请日：2019-06-06

Applicant: Micron Technology, Inc.

Inventor： Ying Rui ,  Tong Liu ,  Yi Fang Lee ,  Davide Colombo ,  Silvia Borsari ,  Austin Johnson

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/768 ,  H01L27/11502

Abstract: A method used in fabrication of integrated circuitry comprises forming metal material outwardly of a substrate. At least a majority (i.e., up to and including 100%) of the metal material contains ruthenium in at least one of elemental-form, metal compound-form, or alloy-form. A masking material is formed outwardly of the ruthenium-containing metal material. The masking material comprises at least one of nine specifically enumerated materials or category of materials. The masking material is used as a mask while etching through an exposed portion of the ruthenium-containing metal material to form a feature of integrated circuitry that comprises the ruthenium-containing metal material.