公开(公告)号：US11462281B1

公开(公告)日：2022-10-04

申请号：US17307443

申请日：2021-05-04

Applicant: Micron Technology, Inc.

Inventor： Lawrence Celso Miranda ,  Eric N. Lee ,  Tong Liu ,  Sheyang Ning ,  Cobie B. Loper ,  Ugo Russo

IPC: G11C16/12 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/06

Abstract: Control logic in a memory device identifies a first group of wordlines associated with a first subset of memory cells of a set of memory cells to be programmed. A first dynamic start voltage operation including a first set of programming pulses and a first set of program verify operations is executed on a first portion of the first subset of memory cells to identify a first dynamic start voltage level, the executing of the first dynamic start voltage operation includes causing the first set of programming pulses to be applied to at least a portion of the first group of wordlines. A second set of programming pulses including at least one programming pulse having the first dynamic start voltage level are caused to be applied to the first group of wordlines to program a second portion of the first subset of memory cells of the set of memory cells. A second group of wordlines associated with a second subset of memory cells to be programmed is identified. A second dynamic start voltage operation including a third set of programming pulses and a second set of program verify operations are executed on a first portion of the second subset of memory cells to identify a second dynamic start voltage level.

公开(公告)号：US11664079B2

公开(公告)日：2023-05-30

申请号：US17940338

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Lawrence Celso Miranda ,  Eric N. Lee ,  Tong Liu ,  Sheyang Ning ,  Cobie B. Loper ,  Ugo Russo

IPC: G11C16/12 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/06

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/06

Abstract: Control logic in a memory device executes a first operation comprising a first set of programming pulses and a first set of program verify operations on a first portion of a first subset of memory cells to be programmed to identify a first start voltage level. A second set of programming pulses including at least one programming pulse having the first start voltage level is caused to be applied to program a second portion of the first subset of memory cells. A second operation including a third set of programming pulses and a second set of program verify operations are executed on a first portion of the second subset of memory cells to identify a second start voltage level.

公开(公告)号：US20230005553A1

公开(公告)日：2023-01-05

申请号：US17940338

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Lawrence Celso Miranda ,  Eric N. Lee ,  Tong Liu ,  Sheyang Ning ,  Cobie B. Loper ,  Ugo Russo

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04

Abstract: Control logic in a memory device executes a first operation comprising a first set of programming pulses and a first set of program verify operations on a first portion of a first subset of memory cells to be programmed to identify a first start voltage level. A second set of programming pulses including at least one programming pulse having the first start voltage level is caused to be applied to program a second portion of the first subset of memory cells. A second operation including a third set of programming pulses and a second set of program verify operations are executed on a first portion of the second subset of memory cells to identify a second start voltage level.