公开(公告)号：US11003396B2

公开(公告)日：2021-05-11

申请号：US16289889

申请日：2019-03-01

Applicant: Micron Technology, Inc.

Inventor： Frank F. Ross ,  Matthew A. Prather

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods related to dual speed memory. A memory module can include a number of memory devices that coupled to a host via a number of first ports and coupled to a controller via a number of second ports. The memory module can be configured to transfer data on the first number of ports at a first clock speed and transfer data on the second number of ports at a second clock speed. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports, and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein the first number of memory devices are configured to transfer data between the first number of memory devices and the host at a first clock speed via the first number of ports and the second number of memory devices are configured to transfer data between the first number of memory devices and the second number of memory devices at a second clock speed via the second number of ports.

公开(公告)号：US11003386B2

公开(公告)日：2021-05-11

申请号：US16015042

申请日：2018-06-21

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Thomas H. Kinsley ,  Matthew A. Prather

IPC: G06F3/06 ,  G11C7/10 ,  G11C11/4093

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication. The device may transmit, from the first portion, a signal instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The signal may be provided at an ODT I/O terminal of the first portion coupled to an ODT I/O terminal of the second portion.

公开(公告)号：US10817371B2

公开(公告)日：2020-10-27

申请号：US16237147

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Randall J. Rooney ,  Matthew A. Prather

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/44 ,  G11C11/406 ,  G11C29/42 ,  G11C29/04

Abstract: Methods, systems, and apparatuses for memory (e.g., DRAM) having an error check and scrub (ECS) procedure in conjunction with refresh operations are described. While a refresh operation reads the code words of a memory row, ECS procedures may be performed on some of the sensed code words. When the write portion of the refresh begins, a code word discovered to have errors may be corrected before it is written back to the memory row. The ECS procedure can be incremental across refresh operations, beginning, for example, each ECS at the code word where the pervious ECS for that row left off. The ECS procedure can include an out-of-order (OOO) procedure where ECS is performed more often for certain identified code words.

公开(公告)号：US20200278794A1

公开(公告)日：2020-09-03

申请号：US16289889

申请日：2019-03-01

Applicant: Micron Technology, Inc.

Inventor： Frank F. Ross ,  Matthew A. Prather

IPC: G06F3/06 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods related to dual speed memory. A memory module can include a number of memory devices that coupled to a host via a number of first ports and coupled to a controller via a number of second ports. The memory module can be configured to transfer data on the first number of ports at a first clock speed and transfer data on the second number of ports at a second clock speed. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports, and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein the first number of memory devices are configured to transfer data between the first number of memory devices and the host at a first clock speed via the first number of ports and the second number of memory devices are configured to transfer data between the first number of memory devices and the second number of memory devices at a second clock speed via the second number of ports.

公开(公告)号：US20200242057A1

公开(公告)日：2020-07-30

申请号：US16846146

申请日：2020-04-10

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Matthew A. Prather

IPC: G06F13/16 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3296 ,  G06F5/06

Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.

公开(公告)号：US20200019312A1

公开(公告)日：2020-01-16

申请号：US16290126

申请日：2019-03-01

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  Matthew A. Prather

IPC: G06F3/06

Abstract: Techniques and devices for managing power consumption of a memory system using loopback are described. When a memory system is in a first state (e.g., a deactivated state), a host device may send a signal to change one or more components of the memory system to a second state (e.g., an activated state). The signal may be received by one or more memory devices, which may activate one or more components based on the signal. The one or more memory devices may send a second signal to a power management component, such as a power management integrated circuit (PMIC), using one or more techniques. The second signal may be received by the PMIC using a conductive path running between the memory devices and the PMIC. Based on receiving the second signal or some third signal that is based on the second signal, the PMIC may enter an activated state.

公开(公告)号：US20190369923A1

公开(公告)日：2019-12-05

申请号：US16543482

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Frank F. Ross ,  Randall J. Rooney

IPC: G06F3/06 ,  G11C11/406 ,  G06F13/40

Abstract: Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.

公开(公告)号：US20190279705A1

公开(公告)日：2019-09-12

申请号：US16423427

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Thomas H. Kinsley

IPC: G11C11/4074 ,  G06F13/10

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.

公开(公告)号：US20190065107A1

公开(公告)日：2019-02-28

申请号：US15693095

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather

IPC: G06F3/06

Abstract: A memory device is provided. The memory device includes a memory array, operation circuitry configured to perform a memory operation in the memory array in response to a command received from a connected host device, and delay circuitry configured to delay the performance of the memory operation in response to one or more bits received with the command. The one or more bits indicate a duration by which to delay the performance of the memory operation.

公开(公告)号：US20250078884A1

公开(公告)日：2025-03-06

申请号：US18948310

申请日：2024-11-14

Applicant: Micron Technology, Inc.

Inventor： Sujeet V. Ayyapureddi ,  Brent Keeth ,  Matthew A. Prather

IPC: G11C7/10 ,  G11C5/04 ,  G11C7/22

Abstract: Methods, systems, and devices for buffer configurations for communications between memory dies and a host device are described. A memory device may include a buffer having a first interface coupled with a host device and a second interface coupled with a memory die of the memory device. The first interface may communicate information with the host device at a first frequency and according to a first signaling scheme, and the second interface may communicate information with the memory die at a second frequency and according to a second signaling scheme. The first frequency may be higher than the second frequency, and the second signaling scheme may include a greater quantity of voltage levels than the first signaling scheme.