公开(公告)号：US20210165586A1

公开(公告)日：2021-06-03

申请号：US17174211

申请日：2021-02-11

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: G06F3/06 ,  G06F1/3246 ,  G06F1/3225 ,  G06F11/34

Abstract: A power management integrated circuit (PMIC) capable of operating, in memory systems, as a master control in power management in some situations and operating as a slave control in power management in other situations. For example, when used in a memory system operating on a SATA bus, the PMIC assumes the master control by monitoring the bus signals for entering or existing a sleep mode or a power shutdown mode, communicating to the controller of the memory system to prepare for the respective mode, and when ready, adjusting power states for the mode changes. For example, when used in a memory system operating on a PCIe bus, the PMIC assumes the slave control during a normal mode and a sleep mode, but the master control when the memory system is in a power disable mode in which the controller of the memory system is powered off.

公开(公告)号：US20200058331A1

公开(公告)日：2020-02-20

申请号：US16661904

申请日：2019-10-23

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: G11C5/14 ,  G11C11/4074 ,  G06F1/28 ,  G06F1/30 ,  H03K17/687

Abstract: Disclosed is an improved load switch driver for Power Management Integrated Circuit (PMIC) devices. In one embodiment, a PMIC is disclosed comprising a gate driver, the gate driver connected to the gate of a switch; an operation frequency generator connected to the gate driver and configured to supply a periodic voltage to the gate driver; and a voltage sensor, the voltage sensor connected to the operation frequency generator and the source of the switch, the voltage sensor configured to monitor a drain-source voltage of the switch and lower the frequency of the operation frequency generator to a second frequency in response to detecting a collapse of the drain-source voltage.

公开(公告)号：US10437321B2

公开(公告)日：2019-10-08

申请号：US15919053

申请日：2018-03-12

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: G06F1/3296 ,  G06F12/02 ,  G11C16/26 ,  H01L27/11526 ,  G11C7/20 ,  G11C7/22 ,  H01L27/11521 ,  G11C16/30 ,  G06F1/3234

Abstract: A power management integrated circuit (PMIC) that has multiple sets of circuits to provide certain same power management functionalities in different power modes, such as voltage, current and temperature sensing and/or measuring, generating of reference states or biases to effectuate circuit protection in various conditions, such as under voltages, over voltages, etc. One set of circuits is configured to operate during a normal mode and is optimized for performance, speed and/or accuracy. Another set of circuits is configured to operate during a sleep mode and is optimized for reduced power consumption where the performance, speed and/or accuracy may be inferior to the circuits for the normal mode but the functionality is maintained within the low power consumption constraint.

公开(公告)号：US20190280602A1

公开(公告)日：2019-09-12

申请号：US16397694

申请日：2019-04-29

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: H02M3/335 ,  H01L23/498 ,  G11C5/14 ,  G06F1/30 ,  H02M1/32 ,  H01L23/50

Abstract: A memory system having a non-volatile memory and a power management integrated circuit (PMIC) that has a voltage regulator to apply a voltage on the non-volatile memory during normal operations. During a shutdown process, the PMIC has a bleeder that is activated to reduce the voltage applied on the non-volatile memory to a level that is below a programmable threshold, before allowing the memory system to restart again. During the bleeding operation, a comparator of the PMIC compares the voltage applied to the non-volatile memory and the threshold to determine whether the shutdown process can be terminated for a restart.

公开(公告)号：US10175902B2

公开(公告)日：2019-01-08

申请号：US15194202

申请日：2016-06-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David Matthew Springberg ,  Matthew David Rowley ,  Peter Edward Kaineg

IPC: G06F3/06 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16

Abstract: A solid-state drive (SSD) includes a connector communicatively coupling the SSD to a host device, a controller coupled to the connector, and a memory device. The SSD also include a regulator configured to receive an instruction to enter a low power mode of the SSD, enter the low power mode upon receipt of the instruction, receive an indication to exit the low power mode, and exit the low power mode upon receipt of the indication.